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TC74VHCT74AFN - DUAL D-TYPE FLIP-FLOP WITH PRESET AND CLEAR

Features

  • High speed: fmax = 160 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C.
  • Compatible with TTL inputs: VIL = 0.8 V (max) VIH = 2.0 V (min).
  • Power down protection is provided on all inputs and outputs.
  • Balanced propagation delays: tpLH ≈ tpHL.
  • Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc. ) 74 type. Note: The JEDEC SOP (FN) is not available in Japan. TC74VHCT74AF TC74VHCT74AFN TC74VHCT74AFT.

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Datasheet Details

Part number TC74VHCT74AFN
Manufacturer Toshiba
File Size 171.69 KB
Description DUAL D-TYPE FLIP-FLOP WITH PRESET AND CLEAR
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TC74VHCT74AF/AFN/AFT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT74AF,TC74VHCT74AFN,TC74VHCT74AFT Dual D-Type Flip-Flop with Preset and Clear The TC74VHCT74 is an advanced high speed CMOS D-TYPE FLIP –FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input low. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system.
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