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Toshiba Electronic Components Datasheet

TC9595XBG Datasheet

Display Interface Bridge

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TC9595XBG
CMOS Digital Integrated Circuit Silicon Monolithic
TC9595XBG
Overview
TC9595XBG
TC9595XBG is a bridge device that enables video streaming from a
Host (application or baseband processor) over MIPI® DSISM or DPISM
link to drive DisplayPortTM display panels. TC9595XBG also supports
audio streaming from the host via I2S interface to the Display panels.
TC9595XBG provides a low power bridge solution to efficiently
P-VFBGA80-0707-0.65-001
Weight: 76mg (Typ.)
translate MIPI® DSI or DPI transfers to DisplayPortTM transfers. As the
DisplayPortTM uses fewer wires compared to other existing display panel standards, it simplifies the LCD
connectivity. The effect of using TC9595XBG is to enable existing baseband devices supporting DSI or DPI
streaming to connect to new panels supporting DisplayPortTM interface and also to connect to existing
panels over longer distance using DisplayPortTM adaptors at far-end.
Features
Translates MIPI® DSI/DPI Link video stream
from Host to DisplayPortTM Link data to external
display devices.
The inputs are driven by a DSI Host with 4-Data
Lanes, upto1 Gbps/lane or DPI Host with
16/18/24 bit interface upto154 MHz parallel
clock.
(Optional) Supports HDCP Digital Content
Protection version 1.3 (DisplayPortTM
amendment Rev1.1).
Embeds audio information from the I2S port into
the DisplayPortTM data stream.
The output Interface consists of a DisplayPortTM
Tx with a 2-lane Main Link and AUX-Ch.
Register Configuration: From DSI link or I2C
interface.
Interrupt to host to inform any error status or
status needing attention from Host.
Internal test pattern (color bar) generator for DP
output testing without any video (DSI/DPI) input.
Debug/Test Port: I2C Slave
DSI Receiver
MIPI® DSI: v1.01 / MIPI® D-PHY: v0.90
Compliant.
Up to four (4) Data Lanes with Bi-direction
support on Data Lane 0.
Maximum speed at 1 Gbps/lane.
Supports Burst as well as Non-Burst Mode
Video Data.
- Video data packets are limited to one row per
HSYNC period.
Supports video stream packets for video data
transmission.
Supports generic long packets for accessing
the chip’s register set.
Video input data formats:
- RGB-565, RGB-666 and RGB-888.
- New DSI V1.02 Data Type Support: 16-bit
YCbCr 422
Interlaced video mode is not supported.
DPI Receiver
Up to 16 / 18 / 24 bit parallel data interface.
Maximum speed at 154 MPs (Mpixel per sec).
Video input data formats: RGB-565, RGB-666
and RGB-888.
Only Progressive mode supported.
I2S Audio Interface: Supports one I2S port for
audio streaming from the host to TC9595XBG.
Supports slave mode (BCLK, LRCLK & over-
sampling clock input from Host).
Supports sampling frequencies of 32, 44.1, 48,
88.2, 96, 176.4 & 192 kHz.
Supports up to 2 audio channels.
Supports 16, 18, 20 or 24bits per sample.
Optionally inserts IEC60958 status bits and
preamble bits per channel.
DisplayPortTM Interface: Supports a
DisplayPortTM link from TC9595XBG to display
panels.
High speed serial bridge chip using VESA®
DisplayPortTM 1.1a Standard.
Supports one dual-lane DisplayPortTM port for
high bandwidth applications
Support 1.62 or 2.7 Gbps/lane data rate with
voltage swings @0.4, 0.6, 0.8 or 1.2 V
Support of pre-emphasis levels of 0, 3.5 and
6dB.
© 2018-2020
Toshiba Electronic Devices & Storage Corporation
1 / 20
2020-05-19
Rev.1.0


Toshiba Electronic Components Datasheet

TC9595XBG Datasheet

Display Interface Bridge

No Preview Available !

Supports Audio related Secondary Data
Packets.
AUX channel supported at 1 Mbps.
HPD support through GPIO based interrupts
Enhanced mode supported for content
protection.
(Optional) Support HDCP encryption Version
1.3 with DisplayPortTM amendment Revision
1.1.
Secure ASSR (Alternate Scrambler Seed
Reset) support.
Stream Policy Maker is assumed handled by
the Host (software/firmware).
- Start Link training in response to HPD & read
final Link training status
- Configure DP link for actual video streaming &
start video streaming
Link Policy maker is assumed shared between
the Host and TC9595XBG chip.
- In auto_correction = 0 mode, control link
training
- Initiate Display device capabilities read and
configure TC9595XBG accordingly.
Video timing generation as per panel
requirement.
SSCG with a 30 kHz modulation to reduce EMI.
Built in PRBS7 Generator to test DisplayPortTM
Link.
RGB Parallel Output Interface:
RGB888 output (DisplayPortTM disabled) with
only DSI input supported in this mode
PCLK max. = 100 MHz
Polarity control for PCLK, VSYNC, HSYNC &
DE
I2C Interface:
I2C slave interface for chip register set access
enabled using a boot-strap option.
I2C compliant slave interface support for normal
(100 kHz) and fast mode (400 kHz).
GPIO Interface:
2 bits of GPIO (shared with other digital logic).
Direction controllable by Host I2C accesses.
TC9595XBG
Clock Source:
DisplayPortTM clock source is from an external
clock input or clock from DSI interface (13, 26,
19.2 or 38.4 MHz) – generates all internal &
output clocks to interfacing display devices.
Built-in PLLs generate high-speed
DisplayPortTM link clock requiring no external
components. These PLLs are part of the
DisplayPortTM PHY.
Clock and power management support to
achieve low power states.
Possible modes of Operation:
MODE S21: TC9595XBG uses DisplayPortTM
Tx as single 2-lane DisplayPortTM link to
interface to single DisplayPortTM display device.
Video stream source is from MIPI® DSI Host.
MODE P21: TC9595XBG uses DisplayPortTM
Tx as single 2-lane DisplayPortTM link to
interface to single DisplayPortTM display device.
Video stream source is from MIPI® DPI Host.
MODE S2P: TC9595XBG uses only Parallel
output port and disables DisplayPortTM Tx to
interface to single RGB display device. Video
stream source is from MIPI® DSI Host.
Power supply inputs
Core and MIPI® D-PHY: 1.2 V ± 0.06 V
Digital I/O:
1.8 V ± 0.09 V
DisplayPortTM:
1.8 V ± 0.09 V
DisplayPortTM:
1.2 V ± 0.06 V
Power Consumptions (Typical value based
on estimations)
Power-down mode (DSI-Rx in ULPS, DP PHY
& PLLs disabled, clocks stopped):
- DSI Rx: 0.01 mW
- DP PHY: 2.34 mW
- PLL9:
0.01 mW
- Core:
0.96 mW
- Rest:
0.01 mW
Normal operation (1920 × 1080 resolution with
DSI-Rx in 4-lane @925 Mbps per lane, DP PHY
in dual lane link @2.7 Gbps per lane):
- DSI Rx: 21.79 mW
- DP PHY: 142.70 mW
- PLL9:
2.42 mW
- Core:
87.64 mW
- IOs:
1.68 mW
Package
- 0.65mm ball pitch, 80 balls, 7 × 7 mm BGA
package
© 2018-2020
Toshiba Electronic Devices & Storage Corporation
2 / 20
2020-05-19
Rev.1.0


Part Number TC9595XBG
Description Display Interface Bridge
Maker Toshiba
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TC9595XBG Datasheet PDF






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