• Part: TC9595XBG
  • Description: Display Interface Bridge
  • Manufacturer: Toshiba
  • Size: 534.56 KB
Download TC9595XBG Datasheet PDF
Toshiba
TC9595XBG
TC9595XBG is Display Interface Bridge manufactured by Toshiba.
Overview TC9595XBG is a bridge device that enables video streaming from a Host (application or baseband processor) over MIPI® DSISM or DPISM link to drive Display Port TM display panels. TC9595XBG also supports audio streaming from the host via I2S interface to the Display panels. TC9595XBG provides a low power bridge solution to efficiently translate MIPI® DSI or DPI transfers to Display Port TM transfers. As the P-VFBGA80-0707-0.65-001 Weight: 76mg (Typ.) Display Port TM uses fewer wires pared to other existing display panel standards, it simplifies the LCD connectivity. The effect of using TC9595XBG is to enable existing baseband devices supporting DSI or DPI streaming to connect to new panels supporting Display Port TM interface and also to connect to existing panels over longer distance using Display Port TM adaptors at far-end. Features - Translates MIPI® DSI/DPI Link video stream from Host to Display Port TM Link data to external display devices. - The inputs are driven by a DSI Host with 4-Data Lanes, upto1 Gbps/lane or DPI Host with 16/18/24 bit interface upto154 MHz parallel clock. - Embeds audio information from the I2S port into the Display Port TM data stream. - The output Interface consists of a Display Port TM Tx with a 2-lane Main Link and AUX-Ch. - Register Configuration: From DSI link or I2C interface. - Interrupt to host to inform any error status or status needing attention from Host. - Internal test pattern (color bar) generator for DP output testing without any video (DSI/DPI) input. - Debug/Test Port: I2C Slave - DSI Receiver - MIPI® DSI: v1.01 / MIPI® D-PHY: v0.90 pliant. - Up to four (4) Data Lanes with Bi-direction support on Data Lane 0. - Maximum speed at 1 Gbps/lane. - Supports Burst as well as Non-Burst Mode Video Data. - Video data packets are limited to one row per HSYNC period. - Supports video stream packets for video data transmission. - Supports generic long packets for accessing the chip’s register set. - Video input data...