4. Absolute Maximum Ratings (Note) (Ta = 25 unless otherwise specified)
Drain current (DC)
Drain current (pulsed)
(Tc = 25 )
(t = 10 s)
(t = 10 s)
Single-pulse avalanche energy
Single-pulse avalanche current
-55 to 175
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
When the body or a connecting part of a semiconductor product is subjected to vibration, impact or stress in
actual equipment, bonding fault or device destruction may result.
Therefore, be sure to keep this in mind at the time of structural design.
If a semiconductor product is subject to especially strong vibration, impact or stress, the package or chip may
crack. If stress is applied to a semiconductor chip through the package, changes in the resistance of the chip
may result due to piezoelectric effects, resulting in fluctuation in element characteristics.
Furthermore, if a stress that does not instantly result in damage is applied continually for a long period of time,
product deformation may result, causing defects such as disconnection or element failure.
Thus, at the time of structural design, carefully consider vibration, impact and stress.
Toshiba Electronic Devices & Storage Corporation