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Toshiba Electronic Components Datasheet

TPW1R104PB Datasheet

N-channel MOSFET

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MOSFETs Silicon N-channel MOS (U-MOS-H)
TPW1R104PB
1. Applications
• Automotive
• Motor Drivers
• Switching Voltage Regulators
2. Features
(1) AEC-Q101 qualified
(2) Small, thin package
(3) Low drain-source on-resistance: RDS(ON) = 0.95 m(typ.) (VGS = 10 V)
(4) Low leakage current: IDSS = 10 µA (max) (VDS = 40 V)
(5) Enhancement mode: Vth = 2.0 to 3.0 V (VDS = 10 V, ID = 0.5 mA)
3. Packaging and Internal Circuit
TPW1R104PB
DSOP Advance(WF)M
1, 2, 3: Source
4: Gate
5, 6, 7, 8: Drain
©2016-2020
Toshiba Electronic Devices & Storage Corporation
1
Start of commercial production
2018-08
2020-06-24
Rev.8.0


Toshiba Electronic Components Datasheet

TPW1R104PB Datasheet

N-channel MOSFET

No Preview Available !

TPW1R104PB
4. Absolute Maximum Ratings (Note) (Ta = 25 unless otherwise specified)
Characteristics
Symbol
Rating
Unit
Drain-source voltage
Gate-source voltage
Drain current (DC)
Drain current (pulsed)
Power dissipation
Power dissipation
(Tc = 25 )
(t = 10 s)
(Note 1)
(Note 1)
(Note 6)
(Note 2)
VDSS
VGSS
ID
IDP
PD
40
V
±20
120
A
360
132
W
3.0
Power dissipation
(t = 10 s)
(Note 3)
0.96
Single-pulse avalanche energy
Single-pulse avalanche current
Channel temperature
Storage temperature
(Note 4)
EAS
IAS
(Note 5)
Tch
(Note 5)
Tstg
140
mJ
120
A
175
-55 to 175
Note:
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note:
When the body or a connecting part of a semiconductor product is subjected to vibration, impact or stress in
actual equipment, bonding fault or device destruction may result.
Therefore, be sure to keep this in mind at the time of structural design.
If a semiconductor product is subject to especially strong vibration, impact or stress, the package or chip may
crack. If stress is applied to a semiconductor chip through the package, changes in the resistance of the chip
may result due to piezoelectric effects, resulting in fluctuation in element characteristics.
Furthermore, if a stress that does not instantly result in damage is applied continually for a long period of time,
product deformation may result, causing defects such as disconnection or element failure.
Thus, at the time of structural design, carefully consider vibration, impact and stress.
©2016-2020
Toshiba Electronic Devices & Storage Corporation
2
2020-06-24
Rev.8.0



Part Number TPW1R104PB
Description N-channel MOSFET
Maker Toshiba
Total Page 3 Pages
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