T6B65AFG Datasheet | Toshiba

Features Dot matrix graphic LCD column driver with display RAM Display RAM capacity : 64 lines × 10 pages × 8 bits = 5120 bits (display area) 1 line × 10 pages × 8 bits = 80 bits (flag area) Total = 5200 bits : 80 : 80-family MPU (8-bit) LCD drive outputs Interface RAM data directly echoed to LCD (1) RAM bit data = 1 …………… ON (2) RAM bit data = 0 …………… OFF Duty: Can be controlled by the T6B66BFG. Display OFF functions Various functions X/Y-counter selection, Up/Down mode selection, X-address setting, Y-address setting, Display Start Line setting, “Status Read”, display data read/write Low power consumption Logic power supply CMOS Si-Gate process 100-pin-plastic flat package : 2.7 to 5.5 V 2005-06-01 Block Diagram .. 2005-06-01 Pin Assignment .. 2005-06-01 Pin Functions Pin Name SEG1 to SEG80 CL PM /φ DB0 to DB7 D/I / WR / CE Pin No . 1 to 80 96 95 94 81 to 88 93 92 91 89 90, 97 98, 99, 100 I/O Output Input Input Input I/O Input Input Input Input ― ― Column driver outputs Shift clock pulse Pre-frame signal input Clock signal Data bus Data/instruction select signal input Write select signal input Chip enable signal input Reset signal input: / RST = L Reset state Power supply Power supply for LCD drive (Note 1) (Note 2) (Note 3) Function .. / RST VDD, VSS VLC2, 3, 5 Note 1: D / I = H ……………… Indicates that the data on DB0 to DB7 is display data. D / I = L ……………… Indicates that the data on DB0 to DB7 is control data. Note 2: / WR = H ………..…… Read is selected. / WR = L ………..…… Write is selected. Note 3: When writing………… Data on DB0 to DB7 is latched on the rising edge of / CE. When reading…..…… Data appears at DB0 to DB7 while / CE is LOW. Function of Each Block - Interface The T6B65AFG is equipped with interface logic enabling interfacing to an 8-bit (80-family) MPU. - Input register This register holds 8-bit data from the MPU. Instruction and display data are distinguished by the D / I signal and the 8-bit...