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TC55VZM216AFTN12 - 16-BIT CMOS STATIC RAM

Download the TC55VZM216AFTN12 datasheet PDF. This datasheet also covers the TC55VZM216AJJN variant, as both devices belong to the same 16-bit cmos static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

The TC55VZM216AJJN/AFTN is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144 words by 16 bits.

Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply.

Key Features

  • Fast access time (the following are maximum values) TC55VZM216AJJN/AFTN08:8 ns TC55VZM216AJJN/AFTN10:10 ns TC55VZM216AJJN/AFTN12:12 ns Low-power dissipation (IDDO2) (the following are maximum values) Cycle Time Operation (max) 8 140 10 130 12 120 ns mA.
  • Single power supply voltage of 3.3 V ± 0.3 V Fully static operation All inputs and outputs are LVTTL compatible Output buffer control using OE Data byte control usi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC55VZM216AJJN_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC55VZM216AFTN10 16-BIT CMOS STATIC RAM
TC55VZM216AFTN08 16-BIT CMOS STATIC RAM
TC55VZM216AJJN 16-BIT CMOS STATIC RAM
TC55V16100FT-10 MOS DIGITAL INTEGRATED CIRCUIT SILICON CMOS
TC55V16100FT-12 MOS DIGITAL INTEGRATED CIRCUIT SILICON CMOS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC55VZM216AJJN/AFTN08,10,12 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT CMOS STATIC RAM DESCRIPTION The TC55VZM216AJJN/AFTN is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode, and output enable ( OE ) provides fast memory access. Data byte control signals ( LB , UB ) provide lower and upper byte access. This device is well suited to cache memory applications where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL compatible.