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TC74HCT174AP - Hex D-Type Flip-Flop

Download the TC74HCT174AP datasheet PDF. This datasheet also covers the TC74HCT174AF variant, as both devices belong to the same hex d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Features

  • High speed: fmax = 56 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • Compatible with TTL outputs: VIH = 2.0 V (min) VIL = 0.8 V (max).
  • Wide interfacing ability: LSTTL, NMOS, CMOS.
  • Output drive capability: 10 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Pin and function compatible with 74LS174 Pin Assignment TC74HCT174.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HCT174AF_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Toshiba

Part Number Description
TC74HCT174AF Hex D-Type Flip-Flop
TC74HCT174AFW HEX D-TYPE FLIP-FLOP
TC74HCT138AF 3-to-8 Line Decoder
TC74HCT138AFW 3-TO-8 LINE DECODER
TC74HCT138AP 3-to-8 Line Decoder

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74HCT174AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT174AP, TC74HCT174AF Hex D-Type Flip Flop with Clear The TC74HCT174A is a high speed CMOS D-TYPE FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. Information signals applied to the D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. When the CLR input is held low, the Q outputs are in the low logic level independent of the other inputs.
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