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TC74HCT74AP - Dual D-Type Flip-Flop

Download the TC74HCT74AP datasheet PDF. This datasheet also covers the TC74HCT74AF variant, as both devices belong to the same dual d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Features

  • High speed: fmax = 53 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C.
  • Compatible with TTL outputs: VIH = 2 V (min) VIL = 0.8 V (max).
  • Wide interfacing ability: LSTTL, NMOS, CMOS.
  • Output drive capability: 10 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Pin and function compatible with 74LS74 Pin Assignment TC74HCT74AP T.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HCT74AF_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Toshiba

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74HCT74AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT74AP, TC74HCT74AF Dual D-Type Flip Flop with Preset and Clear The TC74HCT74A is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL , NMOS and CMOS output voltage levels. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CLOCK pulse. CLEAR and PRESET are independent of the CLOCK and are accomplished by setting the applopriate input to an “L” level.
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