TC9447F
Overview
- Incorporates a 1-bit Σ∆-type AD converter (two channels). THD: -82dB, S/N ratio: 95dB (typ.) Incorporates a 1-bit Σ∆-type DA converter (four channels). THD: -85dB, S/N ratio: 100dB (typ.) A ±10-dB attenuator is built into the DA converter output block (two channels only) Each port has a digital input/output (three lead-type) A built-in self-boot function automatically sets the coefficients and register values at initialization. Boot ROM Data bus Multiplier/adder Accumulator Program ROM Coefficient RAM Coefficient ROM Offset RAM Data RAM Operation speed * * *
- : 1024 words × 18 bits : 24 bits : 24 bits × 16 bits + 43 bits → 43 bits : 43 bits (sign extension: 4 bits) : 1024 words × 32 bits : 320 words × 16 bits : 256 words × 16 bits : 64 words × 16 bits : 256 words × 24 bits : 44ns (510-step (approx) operation per cycle at fs = 44.1 kHz) The DSP block specifications are as follows: Weight: 1.57g (typ.) Interface buffer RAM : 32 words × 16 bits Incorporates data delay RAM. Delay RAM : 4096 words × 16 bits (64 kbits) The microcontroller interface can be selected between Standard Transmission mode and I2C bus mode. CMOS silicon structure supports high speed. The package is a 100-pin flat package. 1
