TQ6124 convertor equivalent, 1 gigasample/sec/ 14-bit digital-to-analog convertor.
Figure 1. TQ6124 Block Diagram
* 1Gs/s aggregate bandwidth
LSBs
CLK NCLK D0 D1 D2 D3 D4 D5 D6
Intermediate Bits
D7 D8 D9
MSBs
D10 D11 D12 D13
* 14-bit resolut.
in direct digital synthesis, pixel generation for high-resolution monitors, broadband video generation, and high-speed a.
The TQ6124 registers incoming bits in a master latch array. The value of the four most-significant bits is encoded into an n-of-15 thermometer code while the ten low-order bits pass though an equalizing delay stage. All 25 bits are re-registered in a.
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