W3EG7264S-BD4 Features
* Double-data-rate architecture DDR200, DDR266 DDR333
* JEDEC design speciļ¬cations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned dat
W3EG7264S-AD4_WhiteElectronic.pdf
Datasheet Details
W3EG7264S-BD4, W3EG7264S-AD4
White Electronic
223.42 KB
512mb - 2x32mx72 ddr ecc sdram unbuffered.
This datasheet PDF includes multiple part numbers: W3EG7264S-BD4, W3EG7264S-AD4.
Please refer to the document for exact specifications by model.
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W3EG7264S-BD4 Distributor
