W682388 Layout Guideline Rev 1.3
W682388 Pro-X™ CODEC Layout Guideline
1. W682388 Layout Considerations
The Winbond W682388 Pro-X™ CODEC family is an excellent solution for short loop telephony
applications. Place the components carefully to insure best performance. This document outlines critical
component layout issues. Use it together with the W682388 data sheet and other supporting Pro-X
The W682388 will exhibit high-quality low-noise performance with the appropriate layout design. Pins
52–61 are sensitive current input pins that are susceptible to induced noise. Keep traces between these
pins and their respective components (C7, C8, C10, C11, R13–16, and R18–27) to a minimum length. Do
not route any digital traces near these sensitive traces.
Place the line compensation capacitors, C5, C8, C9, and C12, near their respective TIP and RING output
pins. Place a 0.1 µF ceramic decoupling capacitor as close as possible to each VDD and VBAT power
supply input pin. These are Pin 49 (VDD1), Pin 64 (VDD2), Pin 41 (VDD3), Pin 8 (VDD4), Pin 27 (VDD5)
and Pin 26 (VDDL). Replace the 0.1 µF capacitors at VDD1 and VDD2 with 10 µF ceramic capacitors for
additional noise performance. Refer to the Figure 3 for an example of this layout.
There are two external Tip and Ring capacitors for each channel. They are connected to CT1 (Pin 39), CR1
(Pin 38), CT2 (Pin 10), and CR2 (Pin 11). The capacitor is a 10 µF ceramic (low leakage) capacitor. It is
connected to 3.3V. Route the capacitors directly to the appropriate VDD pin. For example, the CT1 and
CR1 capacitors connect directly to their respective pins. Their shared 3.3V connection is routed directly to
VDD1 before connecting to the main 3.3V supply. The situation is the same for CT2 and CR2, which must
terminate at VDD2.
The AFE transistors QR3/QT3 (SOT-223) and QR1/QT1 (SOT-89) should have exposed copper pads to
help reduce the thermal resistance of these components. The amount of copper used for the heat sink in
combination with the surface area of the PCB will improve the heat dissipation of the transistor package.
One way to increase the copper area when board space is limited is to connect the pad used for the heat
sink by using multiple layers. A top and bottom side can be used with multiple vias connecting them
together. The optimal copper area to heat sink a SOT-223 is 1 sq inch. This approach is similar to heat
sinking used for the QFN package. (Refer to Section 4 on QFN grounding)
Place the resistors for IREF (Pin 13) and the transconductance amplifiers (Pins 3,5,44 and 46) as close as
possible to the part to minimize the trace length. These resistors are R29, R30 and R31.
If more than two layers are used for the overall board circuit, separate analog and digital trace layers may
enhance performance. Digital signals are best applied to a dedicated layer. The ideal approach is to
separate digital layers from analog layers by a power/ground plane.
AN-CS006a_W682388 PCB Layout.doc
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