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W942516AH Datasheet Preview

W942516AH Datasheet

DDR SDRAM

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PRELIMINARY W942516AH
4M × 4 BANKS × 16 BIT DDR SDRAM
GENERAL DESCRIPTION
W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. Using pipelined architecture and 0.175
µm process technology, W942516AH delivers a data bandwidth of up to 286M words per second (-7).
To fully comply with the personal computer industrial standard, W942516AH is sorted into three speed
grades: -7, -75 and -8. The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -
75 is compliant to the DDR266/CL2.5 specification, the -8 is compliant to the DDR200/CL2
specification
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. And Write
and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942516AH is ideal for main memory in
high performance applications.
FEATURES
2.5V ± 0.2V Power Supply
Up to 143 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and CLK )
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2 and 2.5
Burst Length: 2, 4, and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power-Down
Write Data Mask
Write Latency = 1
8K Refresh cycles / 64 mS
Interface: SSTL-2
Packaged: TSOP II 66 pin, 400 x 875mil , 0.65mm pin pitch
KEY PARAMETERS
SYM.
DESCRIPTION
tCK Clock Cycle Time
CL=2
CL=2.5
tRAS Active to Precharge Command Period
tRC Active to Ref/Active Command Period
IDD1 Operation Current (Single bank)
IDD4 Burst Operation Current
IDD6 Self-Refresh Current
MIN.
/MAX.
min.
min.
min.
min.
max.
max.
max.
-7
7.5 nS
7 nS
45 nS
65 nS
110mA
165mA
3mA
-75
8 nS
7.5 nS
45 nS
65 nS
110mA
155mA
3mA
-8
10 nS
8 nS
50 nS
70 nS
100mA
150mA
3mA
Publication Release Date: May 2001
- 1 - Revision .0.0




Winbond

W942516AH Datasheet Preview

W942516AH Datasheet

DDR SDRAM

No Preview Available !

PIN CONFIGURATION (TOP VIEW)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BS0
BS1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
W942516AH
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
55 VDDQ
54 DQ8
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 CLK
45 CLK
44 CKE
43 NC
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
-2-


Part Number W942516AH
Description DDR SDRAM
Maker Winbond
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