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W942516CH Datasheet Preview

W942516CH Datasheet

DDR SDRAM

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W942516CH
4M × 4 BANKS × 16 BIT DDR SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. KEY PARAMETERS ................................................................................................................... 4
4. PIN CONFIGURATION ............................................................................................................... 5
5. PIN DESCRIPTION..................................................................................................................... 6
6. BLOCK DIAGRAM ...................................................................................................................... 7
7. ELECRICAL CHARACTERISTICS ............................................................................................. 8
7.1 Absolute Maximum Ratings ................................................................................................. 8
7.2 Recommended DC Operating Conditions............................................................................ 8
7.3 Capacitance ......................................................................................................................... 9
7.4 Leakage and Output Buffer Characteristics ......................................................................... 9
7.5 DC Characteristics ............................................................................................................. 10
7.6 AC Characteristics and Operating Condition ..................................................................... 11
7.7 AC Test Conditions ............................................................................................................ 13
8. OPERATION MODE ................................................................................................................. 15
8.1 Simplified Truth Table ........................................................................................................ 15
8.2 Function Truth Table .......................................................................................................... 16
8.3 Function Truth Table for CKE ............................................................................................ 19
8.4 Simplified Stated Diagram.................................................................................................. 20
9. FUNCTIONAL DESCRIPTION.................................................................................................. 21
9.1 Power Up Sequence .......................................................................................................... 21
9.2 Command Function............................................................................................................ 21
9.3 Read Operation.................................................................................................................. 24
9.4 Write Operation .................................................................................................................. 24
9.5 Precharge........................................................................................................................... 24
9.6 Burst Termination............................................................................................................... 25
9.7 Refresh Operation.............................................................................................................. 25
9.8 Power Down Mode............................................................................................................. 25
9.9 Mode Register Operation ................................................................................................... 25
10. TIMING WAVEFORMS ............................................................................................................. 29
10.1 Command Input Timing...................................................................................................... 29
10.2 Timing of the CLK Signals.................................................................................................. 29
Publication Release Date: May 20, 2003
- 1 - Revision A2




Winbond

W942516CH Datasheet Preview

W942516CH Datasheet

DDR SDRAM

No Preview Available !

W942516CH
10.3 Read Timing (Burst Length = 4) ......................................................................................... 30
10.4 Write Timing (Burst Length = 4) ......................................................................................... 31
10.5 DM, Data Mask (W942508CH /W942504CH).................................................................... 32
10.6 DM, Data Mask (W942516CH) .......................................................................................... 32
10.7 Mode Register Set (MRS) Timing ...................................................................................... 33
10.8 Extend Mode Register Set (EMRS) Timing........................................................................ 34
10.9 Auto Precharge Timing (Read Cycle, CL = 2).................................................................... 35
10.10 Auto Precharge Timing (Write Cycle)................................................................................. 37
10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) ............................................................... 38
10.12 Burst Read Stop (BL = 8) ................................................................................................... 38
10.13 Read Interrupted by Write & BST (BL = 8)......................................................................... 39
10.14 Read Interrupted by Precharge (BL = 8) ............................................................................ 39
10.15 Write Interrupted by Write (BL = 2, 4, 8) ............................................................................ 40
10.16 Write Interrupted by Read (CL = 2, BL = 8) ....................................................................... 40
10.17 Write Interrupted by Read (CL = 2.5, BL = 4) .................................................................... 41
10.18 Write Interrupted by Precharge (BL = 8) ............................................................................ 41
10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) .......................................................... 42
10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) .......................................................... 42
10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) .......................................................... 43
10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) .......................................................... 43
10.23 Auto Refresh Cycle ............................................................................................................ 44
10.24 Active Power Down Mode Entry and Exit Timing............................................................... 44
10.25 Precharged Power Down Mode Entry and Exit Timing ...................................................... 44
10.26 Self Refresh Entry and Exit Timing .................................................................................... 45
11. PACKAGE DIMENSION ........................................................................................................... 46
12. REVISION HISTORY ................................................................................................................ 47
-2-


Part Number W942516CH
Description DDR SDRAM
Maker Winbond
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