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Winbond

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W949D6KB Datasheet

512Mb Mobile LPDDR

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512Mb Mobile LPDDR
Table of Contents-
1. GENERAL DESCRIPTION .................................................................................................................................4
2. FEATURES ........................................................................................................................................................4
3. ORDER INFORMATION ....................................................................................................................................5
4. BALL CONFIGURATION....................................................................................................................................6
4.1 Ball Assignment: LPDDR x16 ...............................................................................................................6
4.2 Ball Assignment: LPDDR x32 ...............................................................................................................6
5. BALL DESCRIPTION .........................................................................................................................................7
5.1 Signal Descriptions...............................................................................................................................7
5.2 Addressing Table..................................................................................................................................8
6. BLOCK DIAGRAM..............................................................................................................................................9
6.1 Block Diagram ......................................................................................................................................9
6.2 Simplified State Diagram ....................................................................................................................10
7. FUNCTIONAL DESCRIPTION .........................................................................................................................11
7.1 Initialization.........................................................................................................................................11
7.1.1 Initialization Flow Diagram....................................................................................................12
7.1.2 Initialization Waveform Sequence ........................................................................................13
7.2 Mode Register Set Operation .............................................................................................................13
7.3 Mode Register Definition ....................................................................................................................14
7.3.1 Burst Length .........................................................................................................................14
7.3.2 Burst Definition .....................................................................................................................15
7.3.3 Burst Type ............................................................................................................................16
7.3.4 Read Latency .......................................................................................................................16
7.4 Extended Mode Register Description .................................................................................................16
7.4.1 Extended Mode Register Definition ......................................................................................17
7.4.2 Partial Array Self Refresh .....................................................................................................17
7.4.3 Automatic Temperature Compensated Self Refresh ............................................................17
7.4.4 Output Drive Strength...........................................................................................................17
7.5 Status Register Read .........................................................................................................................18
7.5.1 SRR Register Definition........................................................................................................18
7.5.2 Status Register Read Timing Diagram .................................................................................19
7.6 Commands .........................................................................................................................................20
7.6.1 Basic Timing Parameters for Commands .............................................................................20
7.6.2 Truth Table Commands..................................................................................................20
7.6.3 Truth Table - DM Operations................................................................................................21
7.6.4 Truth Table CKE.............................................................................................................21
7.6.5 Truth Table - Current State Bank n - Command to Bank n...................................................22
7.6.6 Truth Table - Current State Bank n, Command to Bank m ...................................................23
8. OPERATION ....................................................................................................................................................25
8.1 Deselect .............................................................................................................................................25
8.2 No Operation ......................................................................................................................................25
8.2.1 NOP Command ....................................................................................................................25
8.3 Mode Register Set..............................................................................................................................26
8.3.1 Mode Register Set Command ..............................................................................................26
8.3.2 Mode Register Set Command Timing...................................................................................26
Publication Release Date: Dec. 11, 2014
Revision: A01-002
-1-




Winbond

W949D6KB Datasheet Preview

W949D6KB Datasheet

512Mb Mobile LPDDR

No Preview Available !

W949D6KB / W949D2KB
8.4 Active..................................................................................................................................................27
8.4.1 Active Command ..................................................................................................................27
8.4.2 Bank Activation Command Cycle .........................................................................................28
8.5 Read...................................................................................................................................................28
8.5.1 Read Command ...................................................................................................................28
8.5.2 Basic Read Timing Parameters............................................................................................29
8.5.3 Read Burst Showing CAS Latency .......................................................................................30
8.5.4 Read to Read .......................................................................................................................30
8.5.5 Consecutive Read Bursts .....................................................................................................30
8.5.6 Non-Consecutive Read Bursts .............................................................................................31
8.5.7 Random Read Bursts ...........................................................................................................32
8.5.8 Read Burst Terminate ..........................................................................................................32
8.5.9 Read to Write .......................................................................................................................33
8.5.10 Read to Precharge ...............................................................................................................34
8.5.11 Burst Terminate of Read ......................................................................................................35
8.6 Write ...................................................................................................................................................35
8.6.1 Write Command ...................................................................................................................35
8.6.2 Basic Write Timing Parameters ............................................................................................36
8.6.3 Write Burst (min. and max. tDQSS)......................................................................................37
8.6.4 Write to Write........................................................................................................................37
8.6.5 Concatenated Write Bursts...................................................................................................38
8.6.6 Non-Concatenated Write Bursts...........................................................................................38
8.6.7 Random Write Cycles...........................................................................................................39
8.6.8 Write to Read .......................................................................................................................39
8.6.9 Non-Interrupting Write to Read.............................................................................................39
8.6.10 Interrupting Write to Read ....................................................................................................40
8.6.11 Write to Precharge ...............................................................................................................40
8.6.12 Non-Interrupting Write to Precharge.....................................................................................40
8.6.13 Interrupting Write to Precharge ............................................................................................41
8.7 Precharge...........................................................................................................................................41
8.7.1 Precharge Command ...........................................................................................................42
8.8 Auto Precharge...................................................................................................................................42
8.9 Refresh Requirements........................................................................................................................42
8.10 Auto Refresh ......................................................................................................................................43
8.10.1 Auto Refresh Command .......................................................................................................43
8.10.2 Auto Refresh Cycles Back-to-Back ......................................................................................43
8.11 Self Refresh........................................................................................................................................44
8.11.1 Self Refresh Command ........................................................................................................44
8.11.2 Self Refresh Entry and Exit ..................................................................................................45
8.12 Power Down .......................................................................................................................................46
8.12.1 Power-Down Entry and Exit..................................................................................................46
8.13 Deep Power Down..............................................................................................................................47
8.13.1 Deep Power-Down Entry and Exit ........................................................................................47
8.14 Clock Stop ..........................................................................................................................................48
8.14.1 Clock Stop Mode Entry and Exit ...........................................................................................48
9. ELECTRICAL CHARACTERISTICS.................................................................................................................49
9.1 Absolute Maximum Ratings ................................................................................................................49
Publication Release Date: Dec. 11, 2014
Revision: A01-002
-2-


Part Number W949D6KB
Description 512Mb Mobile LPDDR
Maker Winbond
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