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W966K6HB Datasheet Preview

W966K6HB Datasheet

CellularRAM

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W966K6HB
32Mb Async./Page,Syn./Burst CellularRAM
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ........................................................................................................ 4
2. FEATURES................................................................................................................................ 4
3. ORDERING INFORMATION ..................................................................................................... 4
4. PIN CONFIGURATION.............................................................................................................. 5
4.1 Ball Assignment................................................................................................................................. 5
5. PIN DESCRIPTION.................................................................................................................... 6
5.1 Signal Description ............................................................................................................................. 6
6. BLOCK DIAGRAM .................................................................................................................... 7
6.1 Block Diagram ................................................................................................................................... 7
6.2 CellularRAM - Interface Configuration Options .................................................................................. 8
7. INSTRUCTION SET................................................................................................................... 9
7.1 Bus Operation ................................................................................................................................... 9
8. FUNCTIONAL DESCRIPTION ................................................................................................ 10
8.1 Power Up Initialization ..................................................................................................................... 10
8.1.1 Power-Up Initialization Timing...................................................................................................................... 10
8.2 Bus Operating Modes...................................................................................................................... 10
8.2.1 Asynchronous Modes ................................................................................................................................... 10
8.2.1.1 READ Operation(ADV# LOW) .................................................................................................................................11
8.2.1.2 WRITE Operation (ADV# LOW)...............................................................................................................................11
8.2.2 Page Mode READ Operation ....................................................................................................................... 12
8.2.2.1 Page Mode READ Operation (ADV# LOW) .............................................................................................................12
8.2.3 BURST Mode Operation .............................................................................................................................. 12
8.2.3.1 Burst Mode READ (4-word burst) ............................................................................................................................13
8.2.3.2 Burst Mode WRITE (4-word burst)...........................................................................................................................14
8.2.3.3 Refresh Collision During Variable-Latency READ Operation ...................................................................................15
8.2.4 Mixed-Mode Operation ................................................................................................................................. 16
8.2.4.1 WAIT Operation .......................................................................................................................................................16
8.2.4.2 Wired-OR WAIT Configuration.................................................................................................................................16
8.2.5 LB#/ UB# Operation ..................................................................................................................................... 17
8.3 Low Power Operation ...................................................................................................................... 17
8.3.1 Standby Mode Operation ............................................................................................................................. 17
8.3.2 Temperature Compensated Refresh............................................................................................................ 17
8.3.3 Partial Array Refresh .................................................................................................................................... 17
8.3.4 Deep Power-Down Operation ...................................................................................................................... 17
8.4 Registers ......................................................................................................................................... 18
8.4.1 Access Using CRE ....................................................................................................................................... 18
8.4.1.1 Configuration Register WRITE, Asynchronous Mode Followed by READ ARRAY Operation .................................18
8.4.1.2 Configuration Register WRITE CE# control .......................................................................................................19
8.4.1.3 Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation ...................................20
8.4.1.4 Register READ, Asynchronous Mode Followed by READ ARRAY Operation .........................................................21
8.4.1.5 Register READ, Synchronous Mode Followed by READ ARRAY Operation...........................................................22
8.4.2 Software Access........................................................................................................................................... 23
8.4.2.1 Load Configuration Register ....................................................................................................................................23
8.4.2.2 Read Configuration Register....................................................................................................................................24
8.4.3 Bus Configuration Register .......................................................................................................................... 24
8.4.3.1 Bus Configuration Register Definition ......................................................................................................................25
8.4.3.2 Burst Length (BCR[2:0]) Default = Continuous Burst ...............................................................................................26
8.4.3.3 Burst Wrap (BCR[3]) Default = No Wrap..................................................................................................................26
8.4.3.4 Sequence and Burst Length.....................................................................................................................................27
8.4.3.5 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength.....................................................................28
8.4.3.6 Table of Drive Strength ............................................................................................................................................28
Publication Release Date: Nov. 07, 2014
Revision: A01-002
-1-




Winbond

W966K6HB Datasheet Preview

W966K6HB Datasheet

CellularRAM

No Preview Available !

W966K6HB
8.4.3.7 WAIT Signal in Synchronous Burst Mode............................................................................................................28
8.4.3.8 WAIT Config. (BCR[8]).............................................................................................................................................28
8.4.3.9 WAIT Polarity (BCR[10]) ..........................................................................................................................................28
8.4.3.10 WAIT Configuration During Burst Operation ..........................................................................................................29
8.4.3.11 WAIT Function by Configuration (WC) Lat=2, WP=0 .......................................................................................29
8.4.3.12 Latency Counter (BCR[13:11])...............................................................................................................................30
8.4.3.13 Initial Access Latency (BCR[14])............................................................................................................................30
8.4.3.14 Allowed Latency Counter Settings in Variable Latency Mode ................................................................................30
8.4.3.15 Latency Counter (Variable Initial Latency, No Refresh Collision)...........................................................................31
8.4.3.16 Latency Counter (Variable Initial Latency, With Refresh Collision) ........................................................................31
8.4.3.17 Allowed Latency Counter Settings in Fixed Latency Mode ....................................................................................32
8.4.3.18 Latency Counter (Fixed Latency) ...........................................................................................................................32
8.4.3.19 Burst Write Always Produces Fixed Latency..........................................................................................................33
8.4.3.20 Burst Interrupt ........................................................................................................................................................33
8.4.3.21 End-of-Row Condition ............................................................................................................................................33
8.4.3.22 Burst Termination or Burst Interrupt At the End of Row .........................................................................................33
8.4.3.23 Operating Mode (BCR[15]) ....................................................................................................................................33
8.4.4 Refresh Configuration Register .................................................................................................................... 34
8.4.4.1 Refresh Configuration Register Mapping .................................................................................................................34
8.4.4.2 Partial Array Refresh (RCR[2:0] Default = Full Array Refresh..................................................................................34
8.4.4.3 Address Patterns for PAR (RCR[4] = 1)...................................................................................................................35
8.4.4.4 Deep Power-Down (RCR[4])....................................................................................................................................35
8.4.4.5 Page Mode Operation (RCR[7])...............................................................................................................................35
8.4.5 Device Identification Register ....................................................................................................................... 35
8.4.5.1 Device Identification Register Mapping ....................................................................................................................35
9. ELECTRICAL CHARACTERISTIC.......................................................................................... 36
9.1 Absolute Maximum DC, AC Ratings ................................................................................................ 36
9.2 Electrical Characteristics and Operating Conditions ........................................................................ 37
9.3 Deep Power-Down Specifications.................................................................................................... 38
9.4 Partial Array Self Refresh Standby Current ..................................................................................... 38
9.5 Capacitance .................................................................................................................................... 38
9.6 AC Input-Output Reference Waveform ............................................................................................ 38
9.7 AC Output Load Circuit.................................................................................................................... 38
10. TIMING REQUIRMENTS ....................................................................................................... 39
10.1 Read, Write Timing Requirements................................................................................................. 39
10.1.1 Asynchronous READ Cycle Timing Requirements .................................................................................... 39
10.1.2 Burst READ Cycle Timing Requirements................................................................................................... 40
10.1.3 Asynchronous WRITE Cycle Timing Requirements................................................................................... 41
10.1.4 Burst WRITE Cycle Timing Requirements ................................................................................................. 42
10.2 TIMING DIAGRAMS...................................................................................................................... 43
10.2.1 Initialization Period ..................................................................................................................................... 43
10.2.2 DPD Entry and Exit Timing Parameters ..................................................................................................... 43
10.2.3 Initialization and DPD Timing Parameters ................................................................................................. 43
10.2.4 Asynchronous READ.................................................................................................................................. 44
10.2.5 Asynchronous READ Using ADV# ............................................................................................................. 45
10.2.6 Page Mode READ ...................................................................................................................................... 46
10.2.7 Single-Access Burst READ Operation-Variable Latency ........................................................................... 47
10.2.8 4-Word Burst READ Operation-Variable Latency ...................................................................................... 48
10.2.9 Single-Access Burst READ Operation-Fixed Latency................................................................................ 49
10.2.10 4-Word Burst READ Operation-Fixed Latency......................................................................................... 50
10.2.11 READ Burst Suspend ............................................................................................................................... 51
10.2.12 Burst READ at End-of-Row (Wrap Off) .................................................................................................... 52
10.2.13 Burst READ Row Boundary Crossing ...................................................................................................... 53
10.2.14 CE#-Controlled Asynchronous WRITE .................................................................................................... 54
Publication Release Date: Nov. 07, 2014
Revision: A01-002
-2-


Part Number W966K6HB
Description CellularRAM
Maker Winbond
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