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W97BH6KB Datasheet Preview

W97BH6KB Datasheet

high-speed SDRAM

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W97BH6KB / W97BH2KB
LPDDR2-S4B 2Gb
Table of Contents-
1. GENERAL DESCRIPTION ............................................................................................................................................ 6
2. FEATURES.................................................................................................................................................................... 6
3. ORDER INFORMATION ................................................................................................................................................ 7
4.
4.1
4.2
PIN CONFIGURATION .................................................................................................................................................. 8
134 Ball VFBGA............................................................................................................................................................. 8
168 Ball WFBGA............................................................................................................................................................ 9
5.
5.1
5.2
PIN DESCRIPTION ..................................................................................................................................................... 10
Basic Functionality ....................................................................................................................................................... 10
Addressing Table ......................................................................................................................................................... 11
6. BLOCK DIAGRAM ....................................................................................................................................................... 12
7. FUNCTIONAL DESCRIPTION..................................................................................................................................... 13
7.1 Simplified LPDDR2 State Diagram .............................................................................................................................. 13
7.1.1
Simplified LPDDR2 Bus Interface State Diagram......................................................................................................... 14
7.2 Power-up, Initialization, and Power-Off ........................................................................................................................ 15
7.2.1
Power Ramp and Device Initialization.......................................................................................................................... 15
7.2.2
Timing Parameters for Initialization.............................................................................................................................. 17
7.2.3
Power Ramp and Initialization Sequence .................................................................................................................... 17
7.2.4
Initialization after Reset (without Power ramp) ............................................................................................................. 18
7.2.5
Power-off Sequence.................................................................................................................................................... 18
7.2.6
Timing Parameters Power-Off ..................................................................................................................................... 18
7.2.7
Uncontrolled Power-Off Sequence .............................................................................................................................. 18
7.3 Mode Register Definition.............................................................................................................................................. 19
7.3.1
Mode Register Assignment and Definition ................................................................................................................... 19
7.3.1.1
Mode Register Assignment ............................................................................................................................... 19
7.3.2
MR0_Device Information (MA[7:0] = 00H) ................................................................................................................... 20
7.3.3
MR1_Device Feature 1 (MA[7:0] = 01H)...................................................................................................................... 20
7.3.3.1
Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC).............................................. 21
7.3.3.2
Non Wrap Restrictions ...................................................................................................................................... 21
7.3.4
MR2_Device Feature 2 (MA[7:0] = 02H)...................................................................................................................... 22
7.3.5
MR3_I/O Configuration 1 (MA[7:0] = 03H) ................................................................................................................... 22
7.3.6
MR4_Device Temperature (MA[7:0] = 04H)................................................................................................................. 22
7.3.7
MR5_Basic Configuration 1 (MA[7:0] = 05H) ............................................................................................................... 23
7.3.8
MR6_Basic Configuration 2 (MA[7:0] = 06H) ............................................................................................................... 23
7.3.9
MR7_Basic Configuration 3 (MA[7:0] = 07H) ............................................................................................................... 23
7.3.10
MR8_Basic Configuration 4 (MA[7:0] = 08H) ............................................................................................................... 23
7.3.11
MR9_Test Mode (MA[7:0] = 09H) ................................................................................................................................ 23
7.3.12
MR10_Calibration (MA[7:0] = 0AH) ............................................................................................................................. 24
7.3.13
MR16_PASR_Bank Mask (MA[7:0] = 10H).................................................................................................................. 24
7.3.14
MR17_PASR_Segment Mask (MA[7:0] = 11H)............................................................................................................ 25
7.3.15
MR32_DQ Calibration Pattern A (MA[7:0] = 20H) ........................................................................................................ 25
7.3.16
MR40_DQ Calibration Pattern B (MA[7:0] = 28H) ........................................................................................................ 25
7.3.17
MR63_Reset (MA[7:0] = 3FH): MRW only ................................................................................................................... 25
7.4 Command Definitions and Timing Diagrams................................................................................................................ 26
7.4.1
Activate Command ...................................................................................................................................................... 26
7.4.1.1
Activate Command Cycle: tRCD = 3, tRP = 3, tRRD = 2 ................................................................................... 26
7.4.1.2
tFAW Timing..................................................................................................................................................... 27
7.4.1.3
Command Input Setup and Hold Timing............................................................................................................ 27
7.4.1.4
CKE Input Setup and Hold Timing .................................................................................................................... 28
7.4.2
Read and Write Access Modes.................................................................................................................................... 28
7.4.3
Burst Read Command ................................................................................................................................................. 28
7.4.3.1
Data Output (Read) Timing (tDQSCKmax)........................................................................................................ 29
7.4.3.2
Data Output (Read) Timing (tDQSCKmin)......................................................................................................... 30
Publication Release Date: Apr. 28, 2016
Revision: A01-001
-1-




Winbond

W97BH6KB Datasheet Preview

W97BH6KB Datasheet

high-speed SDRAM

No Preview Available !

W97BH6KB / W97BH2KB
7.4.3.3
Burst Read: RL = 5, BL = 4, tDQSCK > tCK...................................................................................................... 30
7.4.3.4
7.4.3.5
7.4.3.6
Burst Read: RL = 3, BL = 8, tDQSCK < tCK...................................................................................................... 31
LPDDR2: tDQSCKDL Timing ............................................................................................................................ 31
LPDDR2: tDQSCKDM Timing ........................................................................................................................... 32
7.4.3.7
LPDDR2: tDQSCKDS Timing............................................................................................................................ 32
7.4.3.8
Burst Read Followed by Burst Write: RL = 3, WL = 1, BL = 4............................................................................ 33
7.4.3.9
Seamless Burst Read: RL = 3, BL= 4, tCCD = 2 ............................................................................................... 33
7.4.4
Reads Interrupted by a Read....................................................................................................................................... 34
7.4.4.1
Read Burst Interrupt Example: RL = 3, BL= 8, tCCD = 2................................................................................... 34
7.4.5
Burst Write Operation .................................................................................................................................................. 34
7.4.5.1
Data Input (Write) Timing .................................................................................................................................. 35
7.4.5.2
Burst Write: WL = 1, BL= 4 ............................................................................................................................... 35
7.4.5.3
Burst Wirte Followed by Burst Read: RL = 3, WL= 1, BL= 4.............................................................................. 36
7.4.5.4
Seamless Burst Write: WL= 1, BL = 4, tCCD = 2............................................................................................... 36
7.4.6
7.4.6.1
7.4.7
Writes Interrupted by a Write ....................................................................................................................................... 37
Write Burst Interrupt Timing: WL = 1, BL = 8, tCCD = 2 .................................................................................... 37
Burst Terminate........................................................................................................................................................... 37
7.4.7.1
Burst Write Truncated by BST: WL = 1, BL = 16 ............................................................................................... 38
7.4.7.2
Burst Read Truncated by BST: RL = 3, BL = 16................................................................................................ 38
7.4.8
Write Data Mask.......................................................................................................................................................... 39
7.4.8.1
Write Data Mask Timing.................................................................................................................................... 39
7.4.9
Precharge Operation ................................................................................................................................................... 40
7.4.9.1
Bank Selection for Precharge by Address Bits .................................................................................................. 40
7.4.10
Burst Read Operation Followed by Precharge ............................................................................................................. 40
7.4.10.1
Burst Read Followed by Precharge: RL = 3, BL = 8, RU(tRTP(min)/tCK) = 2 .................................................... 41
7.4.10.2
Burst Read Followed by Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 3 .................................................... 41
7.4.11
Burst Write Followed by Precharge ............................................................................................................................. 42
7.4.11.1
Burst Write Follwed by Precharge: WL = 1, BL = 4............................................................................................ 42
7.4.12
7.4.13
Auto Precharge Operation ........................................................................................................................................... 43
Burst Read with Auto-Precharge ................................................................................................................................. 43
7.4.13.1
Burst Read with Auto-Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 2 ........................................................ 43
7.4.14
Burst Write with Auto-Precharge.................................................................................................................................. 44
7.4.14.1
Burst Write with Auto-Precharge: WL = 1, BL = 4.............................................................................................. 44
7.4.14.2
Precharge & Auto Precharge Clarification ......................................................................................................... 45
7.4.15
Refresh Command ...................................................................................................................................................... 46
7.4.15.1
Command Scheduling Separations Related to Refresh..................................................................................... 47
7.4.16
LPDDR2 SDRAM Refresh Requirements .................................................................................................................... 47
7.4.16.1
Definition of tSRF.............................................................................................................................................. 48
7.4.16.2
Regular, Distributed Refresh Pattern................................................................................................................. 50
7.4.16.3
Allowable Transition from Repetitive Burst Refresh........................................................................................... 50
7.4.16.4
NOT-Allowable Transition from Repetitive Burst Refresh .................................................................................. 51
7.4.16.5
Recommended Self-Refresh Entry and Exit ...................................................................................................... 51
7.4.16.6
All Bank Refresh Operation............................................................................................................................... 52
7.4.16.7
Per Bank Refresh Operation ............................................................................................................................. 52
7.4.17
Self Refresh Operation ................................................................................................................................................ 53
7.4.18
Partial Array Self-Refresh: Bank Masking.................................................................................................................... 54
7.4.19
Partial Array Self-Refresh: Segment Masking.............................................................................................................. 54
7.4.20
Mode Register Read Command .................................................................................................................................. 55
7.4.20.1
Mode Register Read Timing Example: RL = 3, tMRR = 2.................................................................................. 56
7.4.20.2
7.4.20.3
Read to MRR Timing Example: RL = 3, tMRR = 2 ............................................................................................ 57
Burst Write Followed by MRR: RL = 3, WL = 1, BL = 4 ..................................................................................... 57
7.4.21
Temperature Sensor.................................................................................................................................................... 58
7.4.21.1
Temperature Sensor Timing ............................................................................................................................. 59
7.4.21.2
DQ Calibration .................................................................................................................................................. 59
7.4.21.3
MR32 and MR40 DQ Calibration Timing Example: RL = 3, tMRR = 2 ............................................................... 60
7.4.22
Mode Register Write Command................................................................................................................................... 61
Publication Release Date: Apr. 28, 2016
Revision: A01-001
-2-


Part Number W97BH6KB
Description high-speed SDRAM
Maker Winbond
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