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W986432DH Datasheet Preview

W986432DH Datasheet

512K 4 BANKS 32 BITS SDRAM

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PRELIMINARY W986432DH
512K × 4 BANKS × 32 BITS SDRAM
GENERAL DESCRIPTION
W986432DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words × 4 banks × 32 bits. Using pipelined architecture and 0.175 µm process technology,
W986432DH delivers a data bandwidth of up to 800M bytes per second (5). For different application,
W986432DH is sorted into four speed grades: -5, -55, -6, -7,-8.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W986432DH is ideal for main memory in
high performance applications.
FEATURES
3.3V ±0.3V power supply
524288 words × 4 banks × 32 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Sequential and Interleave burst
Burst read, single write operation
Byte data controlled by DQM
Power-down Mode
Auto-precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Packaged in 86-pin TSOP II, 400 mil - 0.50
Publication Release Date: May 2000
- 1 - Revision A0




Winbond

W986432DH Datasheet Preview

W986432DH Datasheet

512K 4 BANKS 32 BITS SDRAM

No Preview Available !

PRELIMINARY W986432DH
PIN CONFIGURATION
512K × 4 BANKS × 32 BITS SDRAM
PIN DESCRIPTION
PIN NAME
A0A10
BS0, BS1
DQ0DQ31
CS
RAS
CAS
WE
FUNCTION
Address
Bank Select
Data Input/
Output
Chip Select
Row Address
Strobe
Column Address
Strobe
Write Enable
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0A10. Column address: A0A7.
A10 is sampled during a precharge command to determine if
all banks are to be precharged or bank selected by BS0, BS1.
Select bank to activate during row address latch time, or bank
to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Command input. When sampled at the rising edge of the
clock RAS , CAS and WE define the operation to be
executed.
Referred to RAS
Referred to RAS
Publication Release Date: May 2000
- 2 - Revision A0


Part Number W986432DH
Description 512K 4 BANKS 32 BITS SDRAM
Maker Winbond
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