W986432DH
Overview
W986432DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words × 4 banks × 32 bits. Using pipelined architecture and 0.175 µm process technology, W986432DH delivers a data bandwidth of up to 800M bytes per second (5).
- 3.3V ±0.3V power supply 524288 words × 4 banks × 32 bits organization Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8, and full page Sequential and Interleave burst Burst read, single write operation Byte data controlled by DQM Power-down Mode Auto-precharge and controlled precharge 4K refresh cycles/64 mS Interface: LVTTL Packaged in 86-pin TSOP II, 400 mil - 0.50 -1- Publication Release Date: May 2000 Revision A0
