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X25128 Datasheet Preview

X25128 Datasheet

SPI Serial E 2 PROM with Block Lock TM Protection

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APPLICATION NOTE
A VA I L A B L E
AN61
128K
X25128
SPI Serial E2PROM with Block LockTM Protection
16K x 8 Bit
FEATURES
2MHz Clock Rate
SPI Modes (0,0 & 1,1)
16K X 8 Bits
—32 Byte Page Mode
Low Power CMOS
—<1µA Standby Current
—<5mA Active Current
2.7V To 5.5V Power Supply
Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
14-Lead SOIC Package
16-Lead SOIC Package
8-Lead PDIP Package
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
DESCRIPTION
The X25128 is a CMOS 131,072-bit serial E2PROM,
internally organized as 16K x 8. The X25128 features
a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple three-wire bus.
The bus signals are a clock input (SCK) plus separate
data in (SI) and data out (SO) lines. Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same
bus.
The X25128 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25128 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25128 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25128 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
128
128
256
16K BYTE
ARRAY
16 X 256
16 X 256
32 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
32 8
Y DECODE
DATA REGISTER
3091 FM F01
©Xicor Inc. 1994, 1995, 1996 Patents Pending
3091-2.9 5/14/97 T2/C0/D2 SH
Characteristics subject to change without notice
1




Xicor

X25128 Datasheet Preview

X25128 Datasheet

SPI Serial E 2 PROM with Block Lock TM Protection

No Preview Available !

X25128
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the
clock input, while data on the SO pin change after the
falling edge of the clock input.
Chip Select (CS)
When CS is high, the X25128 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25128 will
be in the standby power mode. CS low enables the
X25128, placing it in the active power mode. It should
be noted that after power-up, a high to low transition
on CS is required prior to the start of any operation.
Write Protect (WP)
When WP is low and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25128 status register are
disabled, but the part otherwise functions normally.
When WP is held high, all functions, including nonvola-
tile writes operate normally. WP going low while CS is
still low will interrupt a write to the X25128 status
register. If the internal write cycle has already been
initiated, WP going low will have no effect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25128 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set “0”.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought low while SCK is Low. To resume commu-
nication, HOLD is brought high, again while SCK is
low. If the pause feature is not used, HOLD should be
held high at all times.
PIN CONFIGURATION
.344”
CS
SO
NC
NC
NC
WP
VSS
14 Lead SOIC
1 14
2 13
3 12
4 11
X24128
5 10
69
78
.244”
Not to scale
VCC
HOLD
NC
NC
NC
SCK
SI
.394”
CS
SO
NC
NC
NC
NC
WP
VSS
16 Lead SOIC
1 16
2 15
3 14
4 13
X25128
5 12
6 11
7 10
89
VCC
HOLD
NC
NC
NC
NC
SCK
SI
.244”
.430”
CS
SO
WP
VSS
8 Lead PDIP
18
27
X25128
36
45
.325”
VCC
HOLD
SCK
SI
3091 FM 02
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
HOLD
NC
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
3091 FM T01
2


Part Number X25128
Description SPI Serial E 2 PROM with Block Lock TM Protection
Maker Xicor
Total Page 15 Pages
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