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Xicor

X25163 Datasheet Preview

X25163 Datasheet

Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM

No Preview Available !

64K
X25643/45
8K x 8 Bit
32K
X25323/25
4K x 8 Bit
16K
X25163/65
2K x 8 Bit
Programmable Watchdog Timer & VCC Supervisory Circuit w/Serial E2PROM
FEATURES
DESCRIPTION
• Programmable Watchdog Timer
• Low Vcc Detection and Reset Assertion
—Reset Signal Valid to Vcc=1V
• Save Critical Data With Block LockTM Protection
—Block LockTM Protect 0, 1/4, 1/2 or all of
Serial E2PROM Memory Array
• In Circuit Programmable ROM Mode
• Long Battery Life With Low Power Consumption
—<50µA Max Standby Current, Watchdog On
—<1µA Max Standby Current, Watchdog Off
—<5mA Max Active Current during Write
—<400µA Max Active Current during Read
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• 2MHz Clock Rate
• Minimize Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• SPI Modes (0,0 & 1,1)
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• High Reliability
• Available Packages
—14-Lead SOIC (X2564x)
—14-Lead TSSOP (X2532x, X2516x)
—8-Lead SOIC (X2532x, X2516x)
These devices combine three popular functions, Watch-
dog Timer, Supply Voltage Supervision, and Serial
E2PROM Memory in one package. This combination low-
ers system cost, reduces board space requirements, and
increases reliability.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. During a system failure,
the device will respond with a RESET/RESET signal
after a selectable time-out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET/RESET is asserted until Vcc returns to
proper operating levels and stabilizes.
The memory portion of the device is a CMOS Serial
E2PROM array with Xicor’s Block LockTM Protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct WriteTM cell,
providing a minimum endurance of 100,000 cycles per
sector and a minimum data retention of 100 years.
BLOCK DIAGRAM
SI
SO
SCK
CS
RESET/RESET
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
RESET
CONTROL
X - DECODE
LOGIC
STATUS
REGISTER
PAGE DECODE LOGIC
32 8
SERIAL
E2PROM
ARRAY
VCC
LOW
VOLTAGE
SENSE
WATCHDOG
TIMER
WP
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7049 -1.0 6/20/97 T0/C0/D0 SH
PROGRAMMING,
BLOCK LOCK &
ICP ROM CONTROL
1
HIGH
VOLTAGE
CONTROL
7036 FRM 01
Characteristics subject to change without notice




Xicor

X25163 Datasheet Preview

X25163 Datasheet

Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM

No Preview Available !

X25643/45
X25323/25
X25163/65
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
Serial Input (SI)
SI is a serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this pin.
Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present on
the SI pin are latched on the rising edge of the clock input,
while data on the SO pin change after the falling edge of
the clock input.
Chip Select (CS)
When CS is HIGH, the device is deselected and the SO
output pin is at high impedance and unless a nonvolatile
write cycle is underway, the device will be in the standby
power mode. CS LOW enables the device, placing it in
the active power mode. It should be noted that after
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Write Protect (WP)
When WP is low and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the device’s Status Register are
disabled, but the part otherwise functions normally. When
WP is held high, all functions, including nonvolatile writes
to the Status Register operate normally. If an internal
Status Register Write Cycle has already been initiated,
WP going low while WPEN is a “1” will have no effect on
this write. Subsequent write attempts to the Status
Register under these conditions will be disabled.
PIN CONFIGURATION
NC
CS
CS
0.345” SO
WP
VSS
NC
14-LEAD SOIC
1 14
2 13
3 12
X25643/45
4 11
5 10
69
78
0.244”
Not to Scale
NC
V CC
V CC
RESET/RESET
SCK
SI
NC
CS
SO
0.197” WP
VSS
8-LEAD SOIC
18
2 X25323/25 7
X25163/65
36
45
0.244”
V CC
RESET/RESET
SCK
SI
14-LEAD TSSOP
CS
SO
NC
0.200” NC
NC
WP
VSS
1 14
2 13
3 X25323/25 12
4 X25163/65 11
5 10
69
78
0.177”
V CC
RESET/RESET
NC
NC
NC
SCK
SI
7036 FRM 02
The WP pin function is blocked when the WPEN bit in the
Status Register is “0”. This allows the user to install the
device in a system with WP pin grounded and still be able
to program the Status Register. The WP pin functions will
be enabled when the WPEN bit is set to a “1”.
Reset (RESET/RESET)
RESET/RESET is an active LOW/HIGH, open drain out-
put which goes active whenever Vcc falls below the mini-
mum Vcc sense level. It will remain active until Vcc rises
above the minimum Vcc sense level for 200ms. RESET/
RESET will also go active if the Watchdog Timer is
enabled and CS remains either HIGH or LOW longer than
the selectable Watchdog time-out period. A falling edge of
CS will reset the Watchdog Timer.
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
RESET/RESET
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Program Protect Input
Ground
Supply Voltage
Reset Output
7036 FRM T01
2


Part Number X25163
Description Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM
Maker Xicor
Total Page 16 Pages
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