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XC4052XLA Datasheet Preview

XC4052XLA Datasheet

XC4000XLA/XV Field Programmable Gate Arrays

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Product Obsolete/Under Obsolescence
0
XC4000XLA/XV Field Programmable
R Gate Arrays
DS015 (v2.0) March 1, 2013
0 0* Product Specification
XC4000XLA/XV Family Features
Electrical Features
Note: XC4000XLA devices are improved versions of
XC4000XL devices. The XC4000XV devices have the
same features as XLA devices, incorporate additional inter-
connect resources and extend gate capacity to 500,000
system gates. The XC4000XV devices require a separate
2.5V power supply for internal logic but maintain 5V I/O
compatibility via a separate 3.3V I/O power supply. For
additional information about the XC4000XLA/XV device
architecture, refer to the XC4000E/X FPGA Series general
and functional descriptions.
• System-featured Field-Programmable Gate Arrays
- Select-RAMTM memory: on-chip ultra-fast RAM with
- Synchronous write option
- Dual-port RAM option
- Flexible function generators and abundant flip-flops
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• Flexible Array Architecture
• Low-power Segmented Routing Architecture
• Systems-oriented Features
- IEEE 1149.1-compatible boundary scan
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- Unlimited reprogrammability
• Read Back Capability
- Program verification and internal node observability
*Table 1: XC4000XLA Series Field Programmable Gate Arrays
• XLA Devices Require 3.0 - 3.6 V (VCC)
• XV Devices Require 2.3- 2.7 V (VCCINT)
and 3.0 - 3.6 V (VCCIO)
• 5.0 V TTL compatible I/O
• 3.3 V LVTTL, LVCMOS compliant I/O
• 5.0 V and 3.0 V PCI Compliant I/O
• 12 mA or 24 mA Current Sink Capability
• Safe under All Power-up Sequences
• XLA Consumes 40% Less Power than XL
• XV Consumes 65% Less Power than XL
• Optional Input Clamping to VCC (XLA) or VCCIO (XV)
Additional Features
• Footprint Compatible with XC4000XL FPGAs - Lower
cost with improved performance and lower power
• Advanced Technology — 5 layer metal, 0.25 μm CMOS
process (XV) or 0.35 μm CMOS process (XLA)
• Highest Performance — System performance beyond
100 MHz
• High Capacity — Up to 500,000 system gates and
270,000 synchronous SRAM bits
• Low Power — 3.3 V/2.5 V technology plus segmented
routing architecture
• Safe and Easy to Use — Interfaces to any combination
of 3.3 V and 5.0 V TTL compatible devices
Device
Logic
Cells
Max Logic Max. RAM
Typical
Gates
Bits
Gate Range
(No RAM) (No Logic) (Logic and RAM)*
XC4013XLA
1,368
13,000
18,432 10,000 - 30,000
XC4020XLA
1,862
20,000
25,088 13,000 - 40,000
XC4028XLA
2,432
28,000
32,768 18,000 - 50,000
XC4036XLA
3,078
36,000
41,472 22,000 - 65,000
XC4044XLA
3,800
44,000
51,200 27,000 - 80,000
XC4052XLA
4,598
52,000
61,952 33,000 - 100,000
XC4062XLA
5,472
62,000
73,728 40,000 - 130,000
XC4085XLA
7,448
85,000 100,352 55,000 - 180,000
XC40110XV
9,728
110,000 131,072 75,000 - 235,000
XC40150XV
12,312
150,000 165,888 100,000 - 300,000
XC40200XV
16,758
200,000 225,792 130,000 - 400,000
XC40250XV
20,102
250,000 270,848 180,000 - 500,000
* Maximum values of gate range assume 20-30% of CLBs used as RAM
CLB
Matrix
24 x 24
28 x 28
32 x 32
36 x 36
40 x 40
44 x 44
48 x 48
56 x 56
64 x 64
72 x 72
84 x 84
92 x 92
Total
CLBs
576
784
1,024
1,296
1,600
1,936
2,304
3,136
4,096
5,184
7,056
8,464
Number
of
Flip-Flops
1,536
2,016
2,560
3,168
3,840
4,576
5,376
7,168
9,216
11,520
15,456
18,400
Max.
User I/O
192
224
256
288
320
352
384
448
448
448
448
448
Required
Configur-
ation Bits
393,632
521,880
668,184
832,528
1,014,928
1,215,368
1,433,864
1,924,992
2,686,136
3,373,448
4,551,056
5,433,888
6
DS015 (v2.0) March 1, 2013 - Product Specification
6-157




Xilinx

XC4052XLA Datasheet Preview

XC4052XLA Datasheet

XC4000XLA/XV Field Programmable Gate Arrays

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XC4000XLA/XV Field Programmable Gate Arrays
General Description
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of fifteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, increased speed, abundant
routing resources, and new, sophisticated software to
achieve fully automated implementation of complex,
high-density, high-performance designs.
Figure 1: Cross Section of Xilinx 0.25 micron, 5 layer
metal XC4000XV FPGA. Visible features are five layers of
metallization, tungsten plug vias and trench isolation. The
small gaps above the lowest layer are 0.25 micron
polysilicon MOSFET gates. The excellent planarity of each
metal layer is due to the use of “chemical-mechanical
polishing” or CMP. In effect, each layer is ground flat before
a new layer is added.
Technology Advantage
XC4000XLA/XV FPGAs use 5 layer metal silicon technol-
ogy to improve performance while reducing device cost and
power. In addition, IOB enhancements provide full PCI
compliance and the JTAG functionality is expanded.
Low Power Internal Logic
XC4000XV FPGAs incorporate all the features of the XLA
devices but require a separate 2.5V power supply for inter-
nal logic. I/O pads are still driven from a 3.3V power supply.
The 2.5V logic supply is named VCCINT and the 3.3 V IO
supply is named VCCIO.
The XV devices also incorporate additional routing
resources in the form of 8 octal-length segmented routing
channels vertically and horizontally per row and column.
XLA/XV and XL Family Differences
The XC4000XLA/XV families of FPGAs are logically identi-
cal to XC4000EX and XC4000XL FPGAs, however I/O,
configuration logic, JTAG functionality, and performance
have been enhanced. In addition, they deliver:
Improved Performance
XLA/XV devices benefit from advance processing
technology and a reduction in interconnect capacitance
which improves performance over XL devices by more
than 30%.
Lower Power
XLA/XV devices have reduced power requirements
compared to equivalent XL devices.
Shorter routing delays
The smaller die of XLA/XV devices directly reduces
clock delays and the delay of high-fanout signals. The
reduction in clock delay allows improved pin-to-pin I/O
specifications.
Lower Cost
XLA/XV device cost is directly related to the die size
and has been reduced significantly from that of
equivalent XL devices.
Express mode configuration
Express mode configuration is available on the XLA and
XV devices.
IOB Enhancements
12/24 mA Output Drive
The XLA/XV family of FPGAs allow individual IOBs to
be configured as high drive outputs. Each output can be
configured to have 24 mA drive strength as opposed to
the standard default strength of 12 mA.
VCC Clamping Diode
XLA and XV FPGAs have an optional clamping diode
connected from each output to VCC (VCCIO for XV).
When enabled they clamp ringing transients back to the
3.3V supply rail. This clamping action is required in
3.3V PCI applications. VCC clamping is a global option
affecting all I/O pins. If enabled, TTL I/O compatibility is
maintained, but full 5.0 Volt I/O tolerance is sacrificed.
Enhanced ESD protection
An improved ESD structure allows XV devices to safely
pass the stringent 5V PCI (4.2.1.3) ringing test. This
test applies an 11V pulse to each IOB for 11 ns via a 55
ohm resistor.
Full 3.3V and 5.0V PCI compliance
The addition of 12/24 mA drive, optional 3.3V clamping
and improved ESD provides full compliance with either
3.3V or 5.0V PCI specifications.
6-158
DS015 (v2.0) March 1, 2013 - Product Specification


Part Number XC4052XLA
Description XC4000XLA/XV Field Programmable Gate Arrays
Maker Xilinx
Total Page 14 Pages
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