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Fpga Integrated Circuit

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Virtex-5 Family Overview
DS100 (v5.0) February 6, 2009
00
Product Specification
General Description
The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced
Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice
offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic
designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks,
including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-
controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles
with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options.
Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity,
PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance
PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of
performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5
FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength
of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP
designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and
connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and
link/transaction layer capability.
Summary of Virtex-5 FPGA Features
Five platforms LX, LXT, SXT, TXT, and FXT
Virtex-5 LX: High-performance general logic applications
Virtex-5 LXT: High-performance logic with advanced serial
connectivity
Virtex-5 SXT: High-performance signal processing
applications with advanced serial connectivity
Virtex-5 TXT: High-performance systems with double
density advanced serial connectivity
Virtex-5 FXT: High-performance embedded systems with
advanced serial connectivity
Cross-platform compatibility
LXT, SXT, and FXT devices are footprint compatible in the
same package using adjustable voltage regulators
Most advanced, high-performance, optimal-utilization,
FPGA fabric
Real 6-input look-up table (LUT) technology
Dual 5-LUT option
Improved reduced-hop routing
64-bit distributed RAM option
SRL32/Dual SRL16 option
Powerful clock management tile (CMT) clocking
Digital Clock Manager (DCM) blocks for zero delay
buffering, frequency synthesis, and clock phase shifting
PLL blocks for input jitter filtering, zero delay buffering,
frequency synthesis, and phase-matched clock division
36-Kbit block RAM/FIFOs
True dual-port RAM blocks
Enhanced optional programmable FIFO logic
Programmable
- True dual-port widths up to x36
- Simple dual-port widths up to x72
Built-in optional error-correction circuitry
Optionally program each block as two independent 18-Kbit
blocks
High-performance parallel SelectIO technology
1.2 to 3.3V I/O Operation
Source-synchronous interfacing using ChipSync™
technology
Digitally-controlled impedance (DCI) active termination
Flexible fine-grained I/O banking
High-speed memory interface support
Advanced DSP48E slices
25 x 18, two’s complement, multiplication
Optional adder, subtracter, and accumulator
Optional pipelining
Optional bitwise logical functionality
Dedicated cascade connections
Flexible configuration options
SPI and Parallel FLASH interface
Multi-bitstream support with dedicated fallback
reconfiguration logic
Auto bus width detection capability
www.DataSheet.co.kr
System Monitoring capability on all devices
On-chip/Off-chip thermal monitoring
On-chip/Off-chip power supply monitoring
JTAG access to all monitored quantities
Integrated Endpoint blocks for PCI Express Designs
LXT, SXT, TXT, and FXT Platforms
Compliant with the PCI Express Base Specification 1.1
x1, x4, or x8 lane support per block
Works in conjunction with RocketIO™ transceivers
Tri-mode 10/100/1000 Mb/s Ethernet MACs
LXT, SXT, TXT, and FXT Platforms
RocketIO transceivers can be used as PHY or connect to
external PHY using many soft MII (Media Independent
Interface) options
RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s
LXT and SXT Platforms
RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
TXT and FXT Platforms
PowerPC 440 Microprocessors
FXT Platform only
RISC architecture
7-stage pipeline
32-Kbyte instruction and data caches included
Optimized processor interface structure (crossbar)
65-nm copper CMOS process technology
1.0V core voltage
High signal-integrity flip-chip packaging available in standard
or Pb-free package options
© 2006–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property
of their respective owners.
DS100 (v5.0) February 6, 2009
Product Specification
www.xilinx.com
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XC5VLX20T Datasheet Preview

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Fpga Integrated Circuit

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Virtex-5 Family Overview
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Table 1: Virtex-5 FPGA Family Members
Device
Configurable Logic Blocks (CLBs)
Block RAM Blocks
Array
(Row x Col)
Virtex-5
Slices(1)
Max
Distributed
RAM (Kb)
DSP48E
Slices(2) 18 Kb(3) 36 Kb
Max
(Kb)
PowerPC
CMTs(4) Processor
Blocks
Endpoint
Blocks for
PCI
Express
Ethernet
MACs(5)
Max RocketIO
Transceivers(6) Total
GTP
I/O
GTX Banks(8)
Max
User
I/O(7)
XC5VLX30
80 x 30 4,800
320
32 64 32 1,152 2
N/A
N/A N/A N/A N/A 13 400
XC5VLX50 120 x 30 7,200
480
48 96 48 1,728 6
N/A
N/A N/A N/A N/A 17 560
XC5VLX85 120 x 54 12,960 840 48 192 96 3,456 6 N/A N/A N/A N/A N/A 17 560
XC5VLX110 160 x 54 17,280 1,120
64 256 128 4,608 6
N/A
N/A N/A N/A N/A 23 800
XC5VLX155 160 x 76 24,320 1,640 128 384 192 6,912 6 N/A N/A N/A N/A N/A 23 800
XC5VLX220 160 x 108 34,560 2,280 128 384 192 6,912 6 N/A N/A N/A N/A N/A 23 800
XC5VLX330 240 x 108 51,840 3,420 192 576 288 10,368 6 N/A N/A N/A N/A N/A 33 1,200
XC5VLX20T 60 x 26 3,120
210
24 52 26 936 1
N/A
1
2
4 N/A
7 172
XC5VLX30T 80 x 30 4,800
320
32 72 36 1,296 2
N/A
1
4 8 N/A 12 360
XC5VLX50T 120 x 30 7,200
480
48 120 60 2,160 6
N/A
1
4 12 N/A 15 480
XC5VLX85T 120 x 54 12,960 840
48 216 108 3,888 6
N/A
1
4 12 N/A 15 480
XC5VLX110T 160 x 54 17,280 1,120
64 296 148 5,328 6
N/A
1
4 16 N/A 20 680
XC5VLX155T 160 x 76 24,320 1,640 128 424 212 7,632 6
N/A
1
4 16 N/A 20 680
XC5VLX220T 160 x 108 34,560 2,280 128 424 212 7,632 6
N/A
1
4 16 N/A 20 680
XC5VLX330T 240 x 108 51,840 3,420 192 648 324 11,664 6
N/A
1
4 24 N/A 27 960
XC5VSX35T 80 x 34 5,440
520
192 168 84 3,024 2
N/A
1
4 8 N/A 12 360
XC5VSX50T 120 x 34 8,160
780
288 264 132 4,752 6
N/A
1
4 12 N/A 15 480
XC5VSX95T 160 x 46 14,720 1,520 640 488 244 8,784 6
N/A
1
4 16 N/A 19 640
XC5VSX240T 240 x 78 37,440 4,200 1,056 1,032 516 18,576 6
N/A
1
4 24 N/A 27 960
XC5VTX150T 200 x 58 23,200
XC5VTX240T 240 x 78 37,440
1,500
2,400
80
456
228
8,208
www.DataSheet.co.kr
6
96 648 324 11,664 6
N/A
N/A
1
1
4 N/A 40 20 680
4 N/A 48 20 680
XC5VFX30T 80 x 38 5,120
380
64 136 68 2,448 2
1
1
4 N/A 8
12 360
XC5VFX70T 160 x 38 11,200 820
128 296 148 5,328 6
1
3 4 N/A 16 19 640
XC5VFX100T 160 x 56 16,000 1,240 256 456 228 8,208 6
2
3 4 N/A 16 20 680
XC5VFX130T 200 x 56 20,480 1,580 320 596 298 10,728 6
2
3 6 N/A 20 24 840
XC5VFX200T 240 x 68 30,720 2,280 384 912 456 16,416 6
2
4 8 N/A 24 27 960
Notes:
1. Virtex-5 FPGA slices are organized differently from previous generations. Each Virtex-5 FPGA slice contains four LUTs and four flip-flops (previously
it was two LUTs and two flip-flops.)
2. Each DSP48E slice contains a 25 x 18 multiplier, an adder, and an accumulator.
3. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18-Kbit blocks.
4. Each Clock Management Tile (CMT) contains two DCMs and one PLL.
5. This table lists separate Ethernet MACs per device.
6. RocketIO GTP transceivers are designed to run from 100 Mb/s to 3.75 Gb/s. RocketIO GTX transceivers are designed to run from 150 Mb/s to
6.5 Gb/s.
7. This number does not include RocketIO transceivers.
8. Includes configuration Bank 0.
2
www.xilinx.com
DS100 (v5.0) February 6, 2009
Product Specification
Datasheet pdf - http://www.DataSheet4U.net/


Part Number XC5VLX20T
Description Fpga Integrated Circuit
Maker Xilinx
Total Page 13 Pages
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