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XC5VLX85 - Platform Flash In-System Programmable Configuration PROMS

Download the XC5VLX85 datasheet PDF. This datasheet also covers the XC5VLX110 variant, as both devices belong to the same platform flash in-system programmable configuration proms family and are provided as variant models within a single manufacturer datasheet.

Description

Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs.

Available in 1 to 32 Megabit (Mbit) densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams.

Features

  • In-System Programmable PROMs for Configuration of Xilinx FPGAs Low-Power Advanced CMOS NOR FLASH Process Endurance of 20,000 Program/Erase Cycles Operation over Full Industrial Temperature Range (.
  • 40°C to +85°C) Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing JTAG Command Initiation of Standard FPGA Configuration Cascadable for Storing Longer or Multiple Bitstreams Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ) I/O Pi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (XC5VLX110_Xilinx.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number XC5VLX85
Manufacturer Xilinx (now AMD)
File Size 647.55 KB
Description Platform Flash In-System Programmable Configuration PROMS
Datasheet download datasheet XC5VLX85 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
R Platform Flash In-System Programmable Configuration PROMS Product Specification DS123 (v2.9) May 09, 2006 0 Features • • • • In-System Programmable PROMs for Configuration of Xilinx FPGAs Low-Power Advanced CMOS NOR FLASH Process Endurance of 20,000 Program/Erase Cycles Operation over Full Industrial Temperature Range (–40°C to +85°C) Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing JTAG Command Initiation of Standard FPGA Configuration Cascadable for Storing Longer or Multiple Bitstreams Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ) I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V Design Support Using the Xilinx Alliance ISE and Foundation ISE Series Software Packages • • XCF01S/XCF02S/XCF04S ♦ ♦ ♦ 3.
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