XC7Z045 Datasheet | Xilinx

Overview DS190 (v1.11.1) July 2, 2018 Product Specification Zynq-7000 So C First Generation Architecture The Zynq®-7000 family is based on the Xilinx So C architecture. These products integrate a feature -rich dual-core or single-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. Processing System (PS) ARM Cortex-A9 Based Application Processor Unit (APU) - 2.5 DMIPS/MHz per CPU - CPU frequency: Up to 1 GHz - Coherent multiprocessor support - ARMv7-A architecture - Trust Zone® security - Thumb®-2 instruction set - Jazelle® RCT execution Environment Architecture - NEON™ media-processing engine - Single and double precision Vector Floating Point Unit (VFPU) - Core Sight™ and Program Trace Macrocell (PTM) - Timer and Interrupts - Three watchdog timers - One global timer - Two triple-timer counters Caches - 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU) - 512 KB 8-way set-associative Level 2 cache (shared between the CPUs) - Byte-parity support On-Chip Memory - On-chip boot ROM - 256 KB on-chip RAM (OCM) - Byte-parity support External Memory Interfaces - Multiprotocol dynamic memory controller - 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 memories - ECC support in 16-bit mode - 1GB of address space using single rank of 8-, 16-, or 32-bit-wide memories - Static memory interfaces - 8-bit SRAM data bus with up to 64 MB support - Parallel NOR flash support - ONFI1.0 NAND flash support (1-bit ECC) - 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit) serial NOR...