XC7Z014S Overview
• 2.5 DMIPS/MHz per CPU • CPU frequency: Up to 1 GHz • Coherent multiprocessor support • ARMv7-A architecture • TrustZone® security • Thumb®-2 instruction set • Jazelle® RCT execution Environment Architecture • NEON™ media-processing engine • Single and double precision Vector Floating Point Unit (VFPU) • CoreSight™ and Program Trace Macrocell (PTM) • Timer and Interrupts • Three watchdog timers • One global timer • Two triple-timer counters • 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU) • 512 KB 8-way set-associative Level 2 cache (shared between the CPUs) • Byte-parity support • On-chip boot ROM • 256 KB on-chip RAM (OCM) • Byte-parity support External Memory Interfaces