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XCF16P Datasheet Preview

XCF16P Datasheet

Platform Flash In-System Programmable Configuration PROMs

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35
R
DS123 (v2.19) June 6, 2016
Platform Flash In-System Programmable
Configuration PROMs
Product Specification
Features
• In-System Programmable PROMs for Configuration of
Xilinx® FPGAs
• Low-Power Advanced CMOS NOR Flash Process
• Endurance of 20,000 Program/Erase Cycles
• Operation over Full Industrial Temperature Range
(–40°C to +85°C)
• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
Support for Programming, Prototyping, and Testing
• JTAG Command Initiation of Standard FPGA
Configuration
• Cascadable for Storing Longer or Multiple Bitstreams
• Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
• I/O Pins Compatible with Voltage Levels Ranging From
1.8V to 3.3V
• Design Support Using the Xilinx ISE® Alliance and
Foundation™ Software Packages
• XCF01S/XCF02S/XCF04S
• 3.3V Supply Voltage
• Serial FPGA Configuration Interface
• Available in Small-Footprint VO20 and VOG20
Packages
• XCF08P/XCF16P/XCF32P
• 1.8V Supply Voltage
• Serial or Parallel FPGA Configuration Interface
• Available in Small-Footprint VOG48, FS48, and
FSG48 Packages
• Design Revision Technology Enables Storing and
Accessing Multiple Design Revisions for
Configuration
• Built-In Data Decompressor Compatible with Xilinx
Advanced Compression Technology
Description
Xilinx introduces the Platform Flash series of in-system
programmable configuration PROMs. Available in
1 to 32 Mb densities, these PROMs provide an easy-to-use,
cost-effective, and reprogrammable method for storing large
Xilinx FPGA configuration bitstreams. The Platform Flash
PROM series includes both the 3.3V XCFxxS PROM and
the 1.8V XCFxxP PROM. The XCFxxS version includes
4 Mb, 2 Mb, and 1 Mb PROMs that support Master Serial
and Slave Serial FPGA configuration modes (Figure 1,
page 2). The XCFxxP version includes 32 Mb, 16 Mb, and
8 Mb PROMs that support Master Serial, Slave Serial,
Master SelectMAP, and Slave SelectMAP FPGA
configuration modes (Figure 2, page 2).
When driven from a stable, external clock, the PROMs can
output data at rates up to 33 MHz. Refer to "AC Electrical
Characteristics," page 16 for timing considerations.
A summary of the Platform Flash PROM family members
and supported features is shown in Table 1.
Table 1: Platform Flash PROM Features
Device
XCF01S
XCF02S
XCF04S
Density
(Mb)
1
2
4
VCCINT
(V)
3.3
3.3
3.3
VCCO Range
(V)
1.8 – 3.3
1.8 – 3.3
1.8 – 3.3
VCCJ Range
(V)
2.5 – 3.3
2.5 – 3.3
2.5 – 3.3
XCF08P
8
1.8 1.8 – 3.3 2.5 – 3.3
XCF16P 16
1.8 1.8 – 3.3 2.5 – 3.3
XCF32P 32
1.8 1.8 – 3.3 2.5 – 3.3
Packages
VO20/VOG20
VO20/VOG20
VO20/VOG20
VO48/VOG48
FS48/FSG48
VO48/VOG48
FS48/FSG48
VO48/VOG48
FS48/FSG48
Program In-system
via JTAG
Serial
Config.
Parallel
Config.
Design
Revisioning
Compression

(1)


Notes:
1. XCF08P supports storage of a design revision only when cascaded with another XCFxxP PROM. See "Design Revisioning," page 8 for details.
© Copyright 2003–2016 Xilinx, Inc. XILINX, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. All other trademarks are the property of their respective owners.
DS123 (v2.19) June 6, 2016
Product Specification
www.xilinx.com
1




Xilinx

XCF16P Datasheet Preview

XCF16P Datasheet

Platform Flash In-System Programmable Configuration PROMs

No Preview Available !

X-Ref Target - Figure 1
R
CLK CE
Platform Flash In-System Programmable Configuration PROMs
OE/RESET
TCK
TMS
TDI
Control
and
JTAG
Interface
Data
Address
Memory
Data
Serial
Interface
TDO
CEO
DATA (D0)
Serial Mode
X-Ref Target - Figure 2FI
CLK
CF
Figure 1: XCFxxS Platform Flash PROM Block Diagram
ds123_01_30603
CE EN_EXT_SEL
OE/RESET BUSY
OSC
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Address
Memory
Data
Decompressor
Serial
or
Parallel
Interface
CLKOUT
CEO
DATA (D0)
(Serial/Parallel Mode)
D[1:7]
(Parallel Mode)
CF REV_SEL [1:0]
Figure 2: XCFxxP Platform Flash PROM Block Diagram
DS123_19_031908
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. With CF High, a
short access time after CE and OE are enabled, data is
available on the PROM DATA (D0) pin that is connected to
the FPGA DIN pin. New data is available a short access
time after each rising clock edge. The FPGA generates the
appropriate number of clock pulses to complete the
configuration.
When the FPGA is in Slave Serial mode, the PROM and the
FPGA are both clocked by an external clock source, or
optionally, for the XCFxxP PROM only, the PROM can be
used to drive the FPGA’s configuration clock.
The XCFxxP version of the Platform Flash PROM also
supports Master SelectMAP and Slave SelectMAP (or
Slave Parallel) FPGA configuration modes. When the FPGA
is in Master SelectMAP mode, the FPGA generates a
configuration clock that drives the PROM. When the FPGA
is in Slave SelectMAP Mode, either an external oscillator
generates the configuration clock that drives the PROM and
the FPGA, or optionally, the XCFxxP PROM can be used to
drive the FPGA’s configuration clock. With BUSY Low and
CF High, after CE and OE are enabled, data is available on
the PROMs DATA (D0-D7) pins. New data is available a
short access time after each rising clock edge. The data is
clocked into the FPGA on the following rising edge of the
CCLK. A free-running oscillator can be used in the Slave
Parallel/Slave SelectMAP mode.
The XCFxxP version of the Platform Flash PROM provides
additional advanced features. A built-in data decompressor
supports utilizing compressed PROM files, and design
revisioning allows multiple design revisions to be stored on
a single PROM or stored across several PROMs. For design
revisioning, external pins or internal control bits are used to
select the active design revision.
Multiple Platform Flash PROM devices can be cascaded to
support the larger configuration files required when
targeting larger FPGA devices or targeting multiple FPGAs
daisy chained together. When utilizing the advanced
features for the XCFxxP Platform Flash PROM, such as
design revisioning, programming files which span cascaded
PROM devices can only be created for cascaded chains
containing only XCFxxP PROMs. If the advanced XCFxxP
features are not enabled, then the cascaded chain can
include both XCFxxP and XCFxxS PROMs.
DS123 (v2.19) June 6, 2016
Product Specification
www.xilinx.com
2


Part Number XCF16P
Description Platform Flash In-System Programmable Configuration PROMs
Maker Xilinx
Total Page 30 Pages
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