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XCV400 Datasheet Preview

XCV400 Datasheet

Virtex Field Programmable Gate Array

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Product Obsolete/Under Obsolescence
0
R Virtex™ 2.5 V
Field Programmable Gate Arrays
DS003-1 (v4.0) March 1, 2013
0 0 Product Specification
Features
• Fast, high-density Field Programmable Gate Arrays
- Densities from 50k to 1M system gates
- System performance up to 200 MHz
- 66-MHz PCI Compliant
- Hot-swappable for Compact PCI
• Multi-standard SelectIO™ interfaces
- 16 high-performance interface standards
- Connects directly to ZBTRAM devices
• Built-in clock-management circuitry
- Four dedicated delay-locked loops (DLLs) for
advanced clock control
- Four primary low-skew global clock distribution
nets, plus 24 secondary local clock nets
• Hierarchical memory system
- LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
- Configurable synchronous dual-ported 4k-bit
RAMs
- Fast interfaces to external high-performance RAMs
• Flexible architecture that balances speed and density
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
- Internal 3-state bussing
- IEEE 1149.1 boundary-scan logic
- Die-temperature sensor diode
• Supported by FPGA Foundation™ and Alliance
Development Systems
- Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
- Wide selection of PC and workstation platforms
• SRAM-based in-system configuration
- Unlimited re-programmability
- Four programming modes
• 0.22 μm 5-layer metal process
• 100% factory tested
Description
The Virtex FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22 μm CMOS process. These
advances make Virtex FPGAs powerful and flexible alterna-
tives to mask-programmed gate arrays. The Virtex family
comprises the nine members shown in Table 1.
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the Virtex family delivers a high-speed and
high-capacity programmable logic solution that enhances
design flexibility while reducing time-to-market.
Table 1: Virtex Field Programmable Gate Array Family Members
Device
Maximum
System Gates CLB Array Logic Cells Available I/O
XCV50
57,906
16x24
1,728
180
XCV100
108,904
20x30
2,700
180
XCV150
164,674
24x36
3,888
260
XCV200
236,666
28x42
5,292
284
XCV300
322,970
32x48
6,912
316
XCV400
468,252
40x60
10,800
404
XCV600
661,111
48x72
15,552
512
XCV800
888,439
56x84
21,168
512
XCV1000
1,124,022
64x96
27,648
512
Block RAM
Bits
32,768
40,960
49,152
57,344
65,536
81,920
98,304
114,688
131,072
Maximum
SelectRAM+™ Bits
24,576
38,400
55,296
75,264
98,304
153,600
221,184
301,056
393,216
© 2001-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-1 (v4.0) March 1, 2013
Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1




Xilinx

XCV400 Datasheet Preview

XCV400 Datasheet

Virtex Field Programmable Gate Array

No Preview Available !

Product Obsolete/Under Obsolescence
Virtex™ 2.5 V Field Programmable Gate Arrays
R
Virtex Architecture
Virtex devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the
Virtex family to accommodate even the largest and most
complex designs.
Virtex FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. In
some modes, the FPGA reads its own configuration data
from an external PROM (master serial mode). Otherwise,
the configuration data is written into the FPGA (Select-
MAP™, slave serial, and JTAG modes).
The standard Xilinx Foundation™ and Alliance Series™
Development systems deliver complete design support for
Virtex, covering every aspect from behavioral and sche-
matic entry, through simulation, automatic design transla-
tion and implementation, to the creation, downloading, and
readback of a configuration bit stream.
Higher Performance
Virtex devices provide better performance than previous
generations of FPGA. Designs can achieve synchronous
system clock rates up to 200 MHz including I/O. Virtex
inputs and outputs comply fully with PCI specifications, and
interfaces can be implemented that operate at 33 MHz or
66 MHz. Additionally, Virtex supports the hot-swapping
requirements of Compact PCI.
Xilinx thoroughly benchmarked the Virtex family. While per-
formance is design-dependent, many designs operated
internally at speeds in excess of 100 MHz and can achieve
200 MHz. Table 2 shows performance data for representa-
tive circuits, using worst-case timing parameters.
Table 2: Performance for Common Circuit Functions
Function
Bits Virtex -6
Register-to-Register
Adder
16 5.0 ns
64 7.2 ns
Pipelined Multiplier
8x8
16 x 16
5.1 ns
6.0 ns
Address Decoder
16
64
4.4 ns
6.4 ns
16:1 Multiplexer
5.4 ns
Parity Tree
9 4.1 ns
18 5.0 ns
36 6.9 ns
Chip-to-Chip
HSTL Class IV
200 MHz
LVTTL,16mA, fast slew
180 MHz
Module 1 of 4
2
www.xilinx.com
1-800-255-7778
DS003-1 (v4.0) March 1, 2013
Product Specification


Part Number XCV400
Description Virtex Field Programmable Gate Array
Maker Xilinx
Total Page 30 Pages
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