XCV50E - Virtex-e Field Programmable Gate Array

This page provides the datasheet information for the XCV50E, a member of the XCV50E-6CS144C Virtex-e Field Programmable Gate Array family.

Description

The Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions.

Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 µm CMOS process.

Features

Fast, High-Density 1.8 V FPGA Family - Densities from 58 k to 4 M system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation - PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz Highly Flexible SelectI/O+™ Technology - Supports 20 high-performance interface standards - Up to 804 singled-ended I/Os or 344 differential I/O pairs for an aggregate bandwidth of > 100 Gb/s Differential Signalling Support - LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL - Differential.

Xilinx

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Datasheet Details

Part number	XCV50E
Manufacturer	Xilinx
File Size	1.49 MB
Description	Virtex-e Field Programmable Gate Array
Datasheet	XCV50E Datasheet
Additional preview pages of the XCV50E datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com 0 R Virtex™-E 1.8 V Field Programmable Gate Arrays 0 0 DS022-1 (v2.3) July 17, 2002 Production Product Specification Features • Fast, High-Density 1.8 V FPGA Family - Densities from 58 k to 4 M system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation - PCI compliant 3.

Published: Jan 23, 2008 |