XPLA3 Description
APPLICATION NOTE 0 CoolRunner™ XPLA3 CPLD Advance Product Specification DS012 (v1.1) March 3, 2000 0.
XPLA3 Key Features
- Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture bines
- both CMOS design and process technologies Advanced 0.35µ five metal layer E2CMOS process
- 1,000 erase/program cycles guaranteed
- 20 years data retention guaranteed 3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface
- Full Boundary Scan Test (IEEE 1149.1) Ultra-low static power of less than 100 µA Simple deterministic timing model Suppo
- 16 product term clocks and four local control term clocks per logic block
- Four global clocks and one universal control term clock per device Excellent pin retention during design changes 5V tole
- Asynchronous macrocell clocking
- Asynchronous macrocell register preset/reset
- Clock enable control per macrocell Four output enable controls per logic block Foldback NAND for synthesis optimization