YGV630 - Advanced Video Display Processor 8

YAMAHA

Datasheet Details

s.
CPU Interface 16 bits or 32 bits Data Bus width selection Byte-write operation with WR3-0_N pin Supports data access in both big-endian and little.
endian formats Direct rendering to the entire video memory space from CPU Prepares interrupt pin Controllable Bus Wait and Bus Ready signals.
Clock Built-in PLL for system clock generation Built-in PLL for dot clock generation.
Analog Video Input 12-channel analog video inputs Supports Composite Video, S Video, Co.

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