YGV630
Overview
- Features □ CPU Interface 16 bits or 32 bits Data Bus width selection Byte-write operation with WR3-0_N pin Supports data access in both big-endian and little-endian formats Direct rendering to the entire video memory space from CPU Prepares interrupt pin Controllable Bus Wait and Bus Ready signals □ Clock Built-in PLL for system clock generation Built-in PLL for dot clock generation □ Analog Video Input 12-channel analog video inputs Supports Composite Video, S Video, Component Video input supports NTSC-M, NTSC-JAPAN, PAL-I,B,G,H,D,N, combination N Supports analog RGB input (supports only progressive scan) Up to 4-line analog RGB connection □ Digital Video Input Supports ITU-R BT.656 Supports Digital RGB (6-bit each) Supports both interlace scan and progressive scan Dot clock of 75MHz or lower Digital RGB (6-bit each) input up to 1 channel or ITU-R BT.656 input up to 2 channels
