Datasheet4U Logo Datasheet4U.com

SP8861 - Low Power Single-Chip Frequency Synthesiser

Description

The programmable divider chain is of AM counter design and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which controls the bulk multi-modulus division.

Features

  • s Improved Digital Phase Detector Eliminates HP28 ‘Dead Band’ Effects s Low Operating Power, Typically 175mW.
  • FPD and FREF outputs are reversed by the phase detector sense bit in the F1/F2 programming word. The s 1.
  • 3GHz Operating Frequency above diagram is correct when the sense bit is low. See s Complete Phase Locked Loop Table 2 and Fig. 7. s High Input Sensitivity VCC1, VEE1.
  • preamplifier and prescaler supplies s Programmed throughThree-Wire Bus www. DataSheet4U. com VCC2, VEE2.

📥 Download Datasheet

Datasheet Details

Part number SP8861
Manufacturer Zarlink Semiconductor
File Size 308.01 KB
Description Low Power Single-Chip Frequency Synthesiser
Datasheet download datasheet SP8861 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
SP8861 13GHz Low Power Single-Chip Frequency Synthesiser Mitel Networks
SP8861HP 13GHz Low Power Single-Chip Frequency Synthesiser Mitel Networks
SP8861NAHP 13GHz Low Power Single-Chip Frequency Synthesiser Mitel Networks
SP886 DECT RF Filters SIPAT
SP8802 3.3GHz 2 fixed Modulus Divider Mitel Networks

Other Datasheets by Zarlink Semiconductor

Part Number Description
SP8802 Modulus Divider
SP8803 Modulus Divider
SP8804 Modulus Divider
SP8808 Modulus Divider
SP8830 1.5GHz / 10 Prescaler

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SP8861 1·3GHz Low Power Single-Chip Frequency Synthesiser Supersedes version in the1996 Professional Products IC Handbook, HB2480 - 3.0 DS3640 - 4.0 April 1998 The SP8861 is a low power single chip synthesiser intended for professional radio applications, containing all the elements (apart from the loop amplifier) required to build a PLL frequency synthesis loop The device is serially programmable by a three-wire data highway and contains three independent buffers to store one reference divider word and two local oscillator divider words. A digital phase detector with two charge pumps, programmable in phase and gain, are provided to improve lock-up performance.
Published: |