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Zarlink Semiconductor

ZL50410 Datasheet Preview

ZL50410 Datasheet

Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch

No Preview Available !

ZL50410
Managed 8-Port 10/100M +
1-Port 10/100/1000M Ethernet Switch
Data Sheet
Features
• Integrated Single-Chip 10/100/1000 Ethernet
Switch
• Eight 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
• One 10/100/1000 Mbps auto-negotiating port
with GMII & MII interface options, that can be
used as a WAN uplink or as a 9th port
• a 10/100 Mbps Fast Ethernet (FE) CPU port
www.DataSheweitt4hUR.ceomverse MII interface option
• Operates stand-alone or can be cascaded with a
second ZL50410 to reach 16 ports
• Embedded 2 Mbits (256 KBytes) internal memory
• supports up to 4 K byte frames
• L2 switching
• MAC address self learning, up to 4 K MAC
addresses using internal table
• Supports IP Multicast with IGMP snooping, up
to 4 K IP Multicast groups
• Supports the following spanning standards
- IEEE 802.1D spanning tree
- IEEE 802.1w rapid spanning tree
• Supports Ethernet multicasting and
broadcasting and flooding control
December 2004
Ordering Information
ZL50410GDC208 Pin LBGA
-40°C to +85°C
• VLAN Support
• Supports port-based VLAN and tagged-based
VLAN (IEEE 802.1Q), up to 4 K VLANs
• Supports both shared VLAN learning (SVL)
and independent VLAN learning (IVL)
• Supports Private VLAN Edge (Protected Ports)
• CPU access supports the following interface
options:
• 8/16-bit parallel and Serial+MII interface in
managed mode
• Serial interface in lightly managed mode, or in
unmanaged mode with optional I2C EEPROM
interface
• Failover Features
• Rapid link failure detection using
hardware-generated heartbeat packets
8/16-bit
or
C Serial
P
U
MII
ZL50410
GMII / MII
8-Port 10/100M + 1G
Ethernet Switch
I2C
EEPROM
10/100/
1000
PHY
RMII / MII / GPSI
Quad
10/100
PHY
Quad
10/100
PHY
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.




Zarlink Semiconductor

ZL50410 Datasheet Preview

ZL50410 Datasheet

Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch

No Preview Available !

ZL50410
Data Sheet
• link failover in less than 50 ms
• Rate Control (both ingress and egress)
• Bandwidth rationing, Bandwidth on demand, SLA (Service Level Agreement)
• Smooth out traffic to uplink port
• Ingress Rate Control
- Back pressure
- Flow Control
- WRED (Weighted Random Early Discard)
• Egress Rate Control
• Down to 16 kbps Rate Control granularity
• Per queue traffic shaper on uplink port
• Packet Filtering and Port Security
• Static address filtering for source and/or destination MAC
• Static MAC address not subject to aging
www.DataSheSeet4cUu.rceommode freezes MAC address learning (each port may independently use this mode)
• Supports port authentication (IEEE 802.1x)
• QoS Support
• Supports IEEE 802.1p/Q Quality of Service with 2 transmission priority queues (4 for uplink port), with
strict priority and/or WFQ service disciplines
• Provides 2 levels of dropping precedence with WRED mechanism
• User controls the WRED thresholds.
• Buffer management: per class and per port buffer reservations
• Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID
• Supports per-system option to enable flow control for best effort frames even on QoS enabled ports
• Classification based on:
• Port based priority
• VLAN Priority field in VLAN tagged frame
• DS/TOS field in IP packet
• UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
• The precedence of the above classifications is programmable
• Supports IEEE 802.3ad link aggregation
• Up to 8 trunk groups, with up to 8 ports per group
• Allows trunking of ports located on cascaded chip
• Supports load sharing among trunk ports based on:
- Source port
- Source and/or destination MAC address
• Supports module hot swap on all ports
• MIB Statistics counters for all ports
• Full Duplex Ethernet IEEE 802.3x Flow Control
• Backpressure flow control for Half Duplex ports
• Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports
• Built-in reset logic triggered by system malfunction
• Built-In Self Test for internal SRAM
• IEEE-1149.1 (JTAG) test port
2
Zarlink Semiconductor Inc.


Part Number ZL50410
Description Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
Maker Zarlink Semiconductor
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ZL50410 Datasheet PDF






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