* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
A3R12E30CBF Datasheet (1.42 MB)
A3R12E30CBF
Zentel
1.42 MB
512mb ddrii synchronous dram.
A3R12E30CBF A3R12E40CBF 512Mb DDRII Synchronous DRAM 512Mb DDRII SDRAM Specification A3R12E30CBF A3R12E40CBF Zentel Electronics Corp. Revision 1.2 .
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