* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
A3R1GE4EGF Datasheet (1.64 MB)
A3R1GE4EGF
Zentel
1.64 MB
1gb ddrii sdram.
A3R1GE4EGF 1Gb DDRII Synchronous DRAM 1Gb DDRII SDRAM Specification A3R1GE4EGF Zentel Electronics Corp. Revision 1.0 Apr., 2010 Specifications
📁 Related Datasheet
A3R1GE40JBF 1Gb DDRII Synchronous DRAM (Zentel)
A3R1GE30JBF 1Gb DDRII Synchronous DRAM (Zentel)
A3R12E30CBF 512Mb DDRII Synchronous DRAM (Zentel)
A3R12E30DBF 512Mb DDRII SDRAM (Zentel)
A3R12E40CBF 512Mb DDRII Synchronous DRAM (Zentel)
A3R12E40DBF 512Mb DDRII SDRAM (Zentel)
A3R56E40ABF 256Mb DDRII Synchronous DRAM (Zentel)
A3-44PA-2SV HEADER CONNECTOR (Hirose Electric)
A3-xxxA-2xx HEADER CONNECTOR (Hirose Electric)
A3010 Cascadable Amplifier (Tyco Electronics)
