* - Vdd=VddQ=2.5V+0.2V (-4, -5E, -5) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands en
A3S28D30FTP Datasheet (202.03 KB)
A3S28D30FTP
Zentel
202.03 KB
128m double data rate synchronous dram.
A3S28D30FTP A3S28D40FTP 128M Double Data Rate Synchronous DRAM 128Mb DDR SDRAM Specification A3S28D30FTP A3S28D40FTP Zentel Electronics Corp. Revisi.
📁 Related Datasheet
A3S28D40FTP 128M Double Data Rate Synchronous DRAM (Zentel)
A3S28D40JTP 128M Double Data Rate Synchronous DRAM (Zentel)
A3S12D30ETP 512Mb DDR SDRAM (Powerchip)
A3S12D40ETP 512Mb DDR SDRAM (Powerchip)
A3S56D30ETP (A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM (Zentel)
A3S56D30FTP 256M Double Data Rate Synchronous DRAM (Zentel)
A3S56D30GTP 256M Double Data Rate Synchronous DRAM (Zentel)
A3S56D40ETP (A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM (Zentel)
A3S56D40FTP 256M Double Data Rate Synchronous DRAM (Zentel)
A3S56D40GTP 256M Double Data Rate Synchronous DRAM (Zentel)
