* - Vdd=VddQ=2.5V+0.2V (-50) - Double data rate architecture ; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on e
A3S64D40GTP Datasheet (1.54 MB)
A3S64D40GTP
Zentel
1.54 MB
64m double data rate synchronous dram.
A3S64D40GTP 64M Double Data Rate Synchronous DRAM 64Mb DDR SDRAM Specification A3S64D40GTP Zentel Electronics Corp. Revision 1.0 Nov., 2012 A3S64D.
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