54ACT11138
54ACT11138 is 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS manufactured by Texas Instruments.
description
Y0 5
17 G2B
The ′ACT11138 circuit is designed to be used in high-performance memory-decoding or datarouting applications requiring very short
NC 6
16 NC
Y1 7
15 Y7
Y2
8 14 9 10 11 12 13
Y6 propagation delay times. In high-performance
Y3 GND
NC Y4 Y5 memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a
- No internal connection fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The 54ACT11138 is characterized for operation over the full military temperature range of
- 55°C to 125°C. The 74ACT11138 is characterized for operation from
- 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
- POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1993, Texas Instruments Incorporated 2- 1
54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A
- D3266, JANUARY 1989
- REVISED APRIL 1993 logic symbols (alternatives)†
15 A
14 B
13 C
G1 G2A G2B
11 10 9
BIN/OCT 1 2 4
&
0 1 2 3 4 5 6 7
16 Y0 1 Y1 2 Y2 3 Y3 5 Y4 6 Y5 7 Y6 8 Y7
15 A
14 B
13...
