54ACT11138 Datasheet Text
54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A
- D3266, JANUARY 1989
- REVISED APRIL 1993
- Designed Specifically for High-Speed
54ACT11138 . . . J PACKAGE
Memory Decoders and Data Transmission
74ACT11138 . . . D, N, OR PW PACKAGE
Systems
(TOP VIEW)
- Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
- Flow-Through Architecture Optimizes
PCB Layout
- Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise t- EPIC (Enhanced-Performance Implanted
Y1 Y2 Y3 GND Y4 Y5 Y6
1 2 3 4 5 6 7
16 Y0 15 A 14 B 13 C 12 VCC 11 G1 10 G2A
CMOS) 1-mm Process
Y7 8
9 G2B
- 650-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic
Small-Outline Packages, Plastic Thin
54ACT11138 . . . FK PACKAGE (TOP VIEW)
B C NC VCC G1
Shrink Small-Outline Packages, Ceramic
Chip Carriers, and Standard Plastic and
Ceramic 300-mil DIPs...