54ACT11138
description
Y0 5
17 G2B
The ′ACT11138 circuit is designed to be used in high-performance memory-decoding or datarouting applications requiring very short
NC 6
16 NC
Y1 7
15 Y7
Y2
8 14 9 10 11 12 13
Y6 propagation delay times. In high-performance
Y3 GND
NC Y4 Y5 memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a
- No internal connection fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one...
