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74AC11074 - Dual D-Type Positive-Edge-Triggered Flip-Flop

Description

This device contains two independent positive-edge-triggered D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs.

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Full PDF Text Transcription

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74AC11074 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS499A − DECEMBER 1986 − REVISED APRIL 1996 D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise D EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N) D, N, OR PW PACKAGE (TOP VIEW) 1PRE 1Q 1Q GND 2Q 2Q 2PRE 1 2 3 4 5 6 7 14 1CLK 13 1D 12 1CLR 11 VCC 10 2CLR 9 2D 8 2CLK description This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs.
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