ADC11C125
FEATURES
- 2 1.1 GHz Full Power Bandwidth
- Internal Sample-and-Hold Circuit
- Low Power Consumption
- Internal Precision 1.0V Reference
- Single-Ended or Differential Clock Modes
- Clock Duty Cycle Stabilizer
- Dual +3.3V and +1.8V Supply Operation
- Power-Down and Sleep Modes
- Offset Binary or 2's plement Output Data
Format
- Pin-patible: ADC14155, ADC12C170,
ADC11C170
- 48-pin WQFN Package, (7x7x0.8mm, 0.5mm
Pin-Pitch)
APPLICATIONS
- High IF Sampling Receivers
- Wireless Base Station Receivers
- Power Amplifier Linearization
- Multi-Carrier, Multi-Mode Receivers
- Test and Measurement Equipment
- munications Instrumentation
- Radar Systems
KEY SPECIFICATIONS
- Resolution 11 Bits
- Conversion Rate 125 MSPS
- SNR (f IN = 70 MHz) 65.5 d BFS (typ)
- SFDR (f IN = 70 MHz) 88.2 d BFS (typ)
- ENOB (f IN = 70 MHz) 10.5 bits (typ)
- Full Power Bandwidth 1.1 GHz (typ)
- Power Consumption 608 m W (typ)
DESCRIPTION
The ADC11C125 is a high-performance CMOS analog-to-digital converter capable of...
