ADS61B23 Datasheet | Texas Instruments

FEATURES - Maximum Sample Rate: 80 MSPS - 12-bit Resolution with No Missing Codes - Buffered Analog Inputs with - Very Low Input Capacitance (< 2 p F) - High DC Resistance (5 kΩ) - 82 d Bc SFDR and 70 d BFS SNR (-1 d BFS or 1.8 Vpp input) - 85 d Bc SFDR (-6 d BFS or 1 Vpp input) - 3.5 d B Coarse Gain and up to 6 d B Programmable Fine Gain for SNR and SFDR Trade-Off - Parallel CMOS and Double Data Rate (DDR) LVDS Output Options - Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 m VPP - Clock Duty Cycle Stabilizer - Internal Reference with Support for External Reference - External Decoupling Eliminated for References - Programmable Output Clock Position and Drive Strength to Ease Data Capture - 3.3 V Analog and 1.8 V to 3.3 V Digital Supply - 32-pin QFN Package (5 mm × 5 mm) - Pin patible 12-Bit Family (ADS612X) - Temperature range - 40°C to 85°C APPLICATIONS - Wireless munications Infrastructure - Software Defined Radio - Power Amplifier Linearization - 802.16d/e - Test and Measurement Instrumentation - High Definition Video - Medical Imaging - Radar Systems DESCRIPTION ADS61B23 is a 12-bit A/D converter (ADC) with a maximum sampling frequency of 80 MSPS. It bines high performance and low power consumption in a pact 32-QFN package. The analog inputs use buffers to isolate the switching transients of the internal sample & hold from the external driving circuit. The buffered inputs present very low input capacitance (< 2p F) & wide bandwidth. This makes it easy to drive them at high input frequencies, pared to an ADC without the input buffers. ADS61B23 has coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges. The digital data outputs are parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture- controls for output clock position and output buffer drive strength, plus LVDS current and internal termination programmability. The output interface type, gain,...