AM625-Q1 Datasheet | Texas Instruments

Features Processor Cores: - Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz - Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC - Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection - Single-core Arm® Cortex®-M4F MCU at up to 400MHz - 256KB SRAM with SECDED ECC - Dedicated Device/Power Manager Multimedia: - Display subsystem - Dual display support - 1920x1080 @ 60fps for each display - 1x 2048x1080 + 1x 1280x720 - Up to 165MHz pixel clock support with Independent PLL for each display - OLDI (4 lanes LVDS - 2x) and DPI (24-bit RGB LVCMOS) - Support safety feature such as freeze frame detection and MISR data check - 3D Graphics Processing Unit - 1 pixel per clock or higher - Fillrate greater than 500Mpixels/sec - >500MTexels/s, >8GFLOPs - Supports at least 2 position layers - Supports up to 2048x1080 @60fps - Supports ARGB32, RGB565 and YUV formats - 2D graphics capable - Open GL ES 3.1, Vulkan 1.2 - One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY - MIPI® CSI-2 v1.3 pliant + MIPI D-PHY 1.2 - Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per lane - ECC verification/correction with CRC check + ECC on RAM - Virtual Channel support (up to 16) - Ability to write stream data directly to DDR via Memory Subsystem: - Up to 816KB of On-chip...