CD54HC163 Overview
Description
Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs regardless of the level of the SPE, PE and TE inputs (and the clock input, CP, in the ’HC161 and ’HCT161 types).
Key Features
- Synchronous Counting and Loading
- Two Count Enable Inputs for n-Bit Cascading
- Look-Ahead Carry for High-Speed Counting
- Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . -55oC to 125oC
- Balanced Propagation Delay and Transition Times
