quad d-type flip-flop.
* Common Clock and Asynchronous Reset on Four D-Type Flip-Flops
* Positive Edge Pulse Triggering
* Complementary Outputs
* Buffered Inputs
* Fanout (O.
advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.
Information at the D input is transferred to the Q, Q outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a co.
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