| Title | |
| Description | This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A ● B in positive logic. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) CD74HCT00M SOIC (14) 8.65 mm × 3.90 mm CD74HCT00E PDIP (14) 19.30 mm × 6.40 mm CD54HCT00J CDIP (14) 19.94 mm × 7.62 mm (1) For all available packages, see the orderable addendum at the end of the data ... |
| Features |
• LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 µA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper dete... |
| Datasheet |
 CD54HCT00J Datasheet - 1.00MB |
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