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CD54HCT132J - Quadruple 2-Input NAND Gates

Download the CD54HCT132J datasheet PDF. This datasheet also covers the CD54HCT132 variant, as both devices belong to the same quadruple 2-input nand gates family and are provided as variant models within a single manufacturer datasheet.

General Description

This device contains four independent 2-input NAND gates.

B in positive logic.

Key Features

  • LSTTL input logic compatible.
  • VIL(max) = 0.8 V, VIH(min) = 2 V.
  • CMOS input logic compatible.
  • II ≤ 1 µA at VOL, VOH.
  • Buffered inputs.
  • 4.5 V to 5.5 V operation.
  • Wide operating temperature range:.
  • 55°C to +125°C.
  • Supports fanout up to 10 LSTTL loads.
  • Significant power reduction compared to LSTTL logic ICs 2.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CD54HCT132-etcTI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Texas Instruments

Part Number Description
CD54HCT132 Quadruple 2-Input NAND Gates
CD54HCT138 High-Speed CMOS Logic 3 to 8-Line Decoder/Demultiplexer Inverting/Noninverting
CD54HCT138F High-Speed CMOS Logic 3 to 8-Line Decoder/Demultiplexer Inverting/Noninverting
CD54HCT139 Dual 2- to 4-Line Decoder/Demultiplexer
CD54HCT10 Triple 3-Input NAND Gates

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.ti.com CD74HCT132, CD54HCT132 CD74HSCCTH1S33299, C– JDA5N4UHARCYT2103221 SCHS399 – JANUARY 2021 CDx4HCT132 Quadruple 2-Input NAND Gates with TTL-Compatible Schmitt-Trigger Inputs 1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 µA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 Description This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A ● B in positive logic.