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CD54HCT30 Datasheet Preview

CD54HCT30 Datasheet

8-Input NAND Gate

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Data sheet acquired from Harris Semiconductor
SCHS121D
August 1997 - Revised September 2003
CD54/74HC30,
CD54/74HCT30
High Speed CMOS Logic
8-Input NAND Gate
[ /Title
(CD54H
C30,
CD74H
C30,
CD74H
CT30)
/Subject
(High
Speed
CMOS
Logic 8-
Features
Description
• Buffered Inputs
Typical Propagation Delay:
CL = 15pF, TA = 25oC
10ns
at
VCC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
The ’HC30 and ’HCT30 each contain an 8-input NAND gate
in one package. They provide the system designer with the
direct implementation of the positive logic 8-input NAND
function. Logic gates utilize silicon gate CMOS technology to
achieve operating speeds similar to LSTTL gates with the
low power consumption of standard CMOS integrated cir-
cuits. All devices have the ability to drive 10 LSTTL loads.
The HCT logic family is functionally pin compatible with the
standard LS logic family.
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER
CD54HC30F3A
CD54HCT30F3A
CD74HC30E
CD74HC30M
CD74HC30MT
CD74HC30M96
CD74HC30NSR
TEMP. RANGE
(oC)
PACKAGE
-55 to 125 14 Ld CERDIP
-55 to 125 14 Ld CERDIP
-55 to 125 14 Ld PDIP
-55 to 125 14 Ld SOIC
-55 to 125 14 Ld SOIC
-55 to 125 14 Ld SOIC
-55 to 125 14 Ld SOP
Pinout
CD54HC30, CD54HCT30 (CERDIP)
CD74HC30 (PDIP, SOIC, SOP, TSSOP)
CD74HCT30 (PDIP, SOIC)
TOP VIEW
CD74HC30PW
CD74HC30PWR
CD74HC30PWT
CD74HCT30E
-55 to 125
-55 to 125
-55 to 125
-55 to 125
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
14 Ld PDIP
A1
B2
C3
D4
E5
F6
GND 7
14 VCC
13 NC
12 H
11 G
10 NC
9 NC
8Y
CD74HCT30M
-55 to 125 14 Ld SOIC
CD74HCT30MT
-55 to 125 14 Ld SOIC
CD74HCT30M96
-55 to 125 14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated.
1




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CD54HCT30 Datasheet Preview

CD54HCT30 Datasheet

8-Input NAND Gate

No Preview Available !

Functional Diagram
CD54/74HC30, CD54/74HCT30
1
A
2
B
3
C
4
D
5
E
6
F
11
G
12
H
8
Y
Y = ABCDEFGH
TRUTH TABLE
INPUTS
A
B
C
D
E
F
G
H
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Irrelevant
OUTPUT
H
H
H
H
H
H
H
H
L
Logic Symbol
1
A
2
B
3
C
4
D
8
Y
5
E
6
F
11
G
12
H
2


Part Number CD54HCT30
Description 8-Input NAND Gate
Maker etcTI
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CD54HCT30 Datasheet PDF






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