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CD54HCT365 - High Speed CMOS Logic Hex Buffer/Line Driver

Download the CD54HCT365 datasheet PDF. This datasheet also covers the CD54HC365 variant, as both devices belong to the same high speed cmos logic hex buffer/line driver family and are provided as variant models within a single manufacturer datasheet.

Description

The ’HC365, ’HCT365, and ’HC366 silicon gate CMOS three-state buffers are general purpose highspeed non-inverting and inverting buffers.

Features

  • Buffered inputs.
  • High current bus driver outputs.
  • Typical propagation delay tPLH, tPHL = 8 ns at VCC = 5 V, CL = 15 pF, TA = 25℃.
  • Fanout (over temperature range).
  • Standard outputs: 10 LSTTL Loads.
  • Bus driver outputs: 15 LSTTL Loads.
  • Wide operating temperature range: -55℃ to 125℃.
  • Balanced propagation delay and transition times.
  • Significant power reduction compared to LSTTL Logic ICs.
  • HC types.
  • 2 V.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CD54HC365-etcTI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CD54HC365, CD74HC365, CD54HCT365 CD74HCT365, CD54HC366, CD74HC366 SCHS180D – NOVEMBER 1997 – REVISED JULY 2022 High Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting 1 Features • Buffered inputs • High current bus driver outputs • Typical propagation delay tPLH, tPHL = 8 ns at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LSTTL Loads – Bus driver outputs: 15 LSTTL Loads • Wide operating temperature range: -55℃ to 125℃ • Balanced propagation delay and transition times • Significant power reduction compared to LSTTL Logic ICs • HC types – 2 V to 6 V operation – High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V • HCT types – 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL = 0.
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