Datasheet Summary
CD54ACT138, CD74ACT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
D Inputs Are TTL-Voltage patible D Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
D Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
D Balanced Propagation Delays D ±24-mA Output Drive Current
- Fanout to 15 F Devices
D SCR-Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
SCHS329A
- JANUARY 2003
- REVISED FEBRUARY 2003
CD54ACT138 . . . F PACKAGE CD74ACT138 . . . E OR M PACKAGE
(TOP VIEW)
A1 B2 C3 G2A 4 G2B 5 G1 6 Y7 7 GND...