HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER
WITH 10 DECODED OUTPUTS
SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008
D Qualified for Automotive Applications
D Significant Power Reduction Compared to
D Fully Static Operation
D Buffered Inputs
D Common Reset
D Positive Edge Clocking
LSTTL Logic ICs
D VCC Voltage = 2 V to 6 V
D High Noise Immunity NIL or NIH = 30% of
VCC, VCC = 5 V
D Typical fMAX = 60 MHz at VCC = 5 V,
CL = 15 pF, TA = 25°C
D Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus Driver Outputs . . . 15 LSTTL Loads
D Balanced Propagation Delay and Transition
M OR PW PACKAGE
The CD74HC4017 is a high-speed silicon-gate
CMOS 5-stage Johnson counter with ten decoded
outputs. Each of the decoded outputs normally is low
and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry
(TC) output transitions low to high after output 9 goes from high to low, and can be used in conjunction with the
clock enable (CE) input to cascade several stages. CE disables counting when in the high state. A master reset
(MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.
−40°C to 125°C
SOIC − M
Tape and reel
TSSOP − PW Tape and reel
† For the most current package and ordering information, see the Package Option Addendum at the
end of this document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
CP CE MR
0 = H, 1−9 = L
↑ L L Increments counter
H ↓ L Increments counter
NOTE: H = high voltage level, L = low voltage level,
X = don’t care, ↑ = transition from low to high
level, ↓ = transition from high to low level
† If n < 5, TC = H, otherwise TC = L
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