SCLS459A - June 2001 - Revised May 2003
High-Speed CMOS Logic
8-Input Multiplexer/Register, Three-State
• Edge-Triggered Data Flip-Flops
- Transparent Select Latches
• Buffered Inputs
• 3-State Complementary Outputs
• Bus Line Driving Capability
TA = 25oC
- Clock to Output = 22ns
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Signiﬁcant Power Reduction Compared to LSTTL
• 4.5V to 5.5V Operation
• Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The CD74HCT356 consists of data selectors/multiplexers that
select one of eight sources. The data select bits (S0, S1, and
S2) are stored in transparent latches that are enabled by a low
latch enable input (LE).
The data is stored in edge-triggered ﬂip-ﬂops that are
triggered by a low-to-high clock transition.
In both types the 3-state outputs are controlled by three
output-enable inputs (OE1, OE2, and OE3).
-55 to 125
20 Ld PDIP
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The sufﬁx 96
denotes tape and reel.
(PDIP or SOIC)
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated