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CD74HCT4094 - 8-Stage Shift and Store Bus Register

Download the CD74HCT4094 datasheet PDF. This datasheet also covers the CD74HC4094 variant, as both devices belong to the same 8-stage shift and store bus register family and are provided as variant models within a single manufacturer datasheet.

Description

The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered tri-state outputs.

The parallel outputs may be connected directly to common bus lines.

Features

  • Buffered inputs.
  • Separate serial outputs synchronous to both positive and negative clock edges for cascading.
  • Fanout (over temperature range).
  • Standard outputs: 10 LSTTL loads.
  • Bus driver outputs: 15 LSTTL loads.
  • Wide operating temp range:.
  • 55°C to 125°C.
  • Balanced propagation delay and transition times.
  • Significant power reduction compared to LSTTL logic ICs.
  • HC types.
  • 2- to 6-V operation.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CD74HC4094-etcTI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES NXP

Other Datasheets by Texas Instruments

Part Number Description
CD74HCT4094E 8-Stage Shift and Store Bus Register
CD74HCT4094M 8-Stage Shift and Store Bus Register
CD74HCT40103 8-Stage Synchronous Down Counters
CD74HCT40105 4-Bit x 16-Word FIFO Register
CD74HCT4020 14-Stage Binary Counter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CD54HC4094, CD74HC4094, CD74HCT4094 SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022 CDx4HC4094, CD74HCT4094 High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State 1 Features • Buffered inputs • Separate serial outputs synchronous to both positive and negative clock edges for cascading • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temp range: −55°C to 125°C • Balanced propagation delay and transition times • Significant power reduction compared to LSTTL logic ICs • HC types – 2- to 6-V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V • HCT types – 4.5- to 5.5-V operation – Direct LSTTL input logic compatibility, VIL= 0.
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